We developed an electroholography unit, which consists of a special-purpose computational chip for holography and a reflective liquid-crystal display (LCD) panel, for a three-dimensional (3D) display. The special-purpose chip can compute a computer-generated hologram of 800×600 grids in size from a 3D object consisting of approximately 400 points in approximately 0.15 seconds. The pixel pitch and resolution of the LCD panel are 12µm and 800×600 grids, respectively. We implemented the special purpose chip and LCD panel on a printed circuit board of approximately 28cm×13cm in size. After the calculation, the computer-generated hologram produced by the special-purpose chip is displayed on the LCD panel. When we illuminate a reference light to the LCD panel, we can observe a 3D animation of approximately 3cm×3cm×3cm in size. In the present paper, we report the electroholographic display unit together with a simple 3D display system.
©2005 Optical Society of America
In recent years, researchers have studied three-dimensional (3D) display systems as potential next-generation display systems. Among the techniques currently being researched in the field of 3D display systems, the computer-generated-hologram(CGH) technique has remarkable features [1, 2]. The CGH technique can reconstruct the light wave of a 3D object correctly, and, as such, has been referred to as the ultimate 3D display system since the birth of holography. However, due to two significant problems, no practical 3D display system using the CGH technique has been developed. One problem is the enormous computational time required for the CGH technique. The formula for computing a CGH is expressed as
Here, the indices α and j show a CGH and a 3D object, where A j is the intensity of the 3D object, λ is the wavelength of the reference light, and p is the sampling interval on the CGH and the 3D object. The parameters xα and yα are the horizontal and vertical coordinates of the CGH, respectively, and x j, y j and z j are the horizontal, vertical and depth coordinates of the 3D object. The parameters x j,yj,xα and yα are normalized by the sampling interval p.
The complexity of the above formula is O(MN), where M is the total sampling number of the CGH and N is the total number of points of the 3D object. For example, for the case in which a low-resolution CGH (M=800×600 grids) is computed from a 3D object with a simple structure (N=1,000 points), the computation requires approximately 10 seconds using a personal computer with a 1.8-GHz Pentium-4 processor. Thus, even when using a computer with general computational ability, the CGH cannot be computed at video rate, i.e., 30 CGHs per second. Furthermore, a high-resolution CGH and a 3D object consisting of several points is required in order to develop a practical electroholographic display. Increasing the resolution of a CGH and the number of points of a 3D object requires increased computational ability.
In the calculation of a CGH, Eq. (1) accounts for most computational cost, because the computational cost for a 3D object is proportional to N, whereas that for a CGH is proportional to MN. In order to solve this problem, several software approaches have been proposed [3, 4, 5].
We have designed and built special-purpose computers for holography, called HORN (HOlo-graphic ReconstructioN), in order to overcome the computational cost of the CGH. HORN computers designed using a pipeline architecture can calculate the light intensities on a CGH at high speed [7, 8, 9]. Thus far, we have constructed four HORN computers, which attained computational speeds several times higher than contemporary personal computers and work-stations.
Another problem is the need for a device that can display at high resolution the interference fringe of a CGH. The interval of the interference fringe of a CGH becomes wavelength-order because holography utilizes the phenomena of diffraction and interference of light waves.
Benton et al. used an acoustic optical modulator (AOM) as a spatial light modulator (SLM). An electroholographic display system with an AOM has only horizontal parallax in principle. A reconstructed 3D object from the system is large, because the diffraction angle of an AOM is wide. However, this optical system becomes a complex because it includes mechanism in the system . On the other hand, an electroholographic display system with an LCD as an SLM has also been developed . An electroholographic display with an LCD can realize full parallax. However, 3D objects reconstructed by the system are small because the diffraction angle is narrow. However, the structure of this optical system is simple without mechanism.
Although transmissive LCDs have been primarily used in this field, in the present study, we use a reflective LCD, which may be referred to as a Liquid Crystal On Silicon (LCOS), because reflective LCDs can generally be made small, compared to transmissive LCDs. The reflective LCD has a high contrast and a minute pixel pitch. Therefore, we can obtain a bright and large 3D object [10, 12].
We developed an electroholographic unit, which has a special-purpose chip for holography based on the HORN computer and a reflective LCD panel on a printed circuit board, for a 3D display system. In the present paper, we report the electroholographic display unit. In Section 2, we describe the electroholographic display unit and experimental results obtained using the unit. In Section 3, we describe our future research plans.
2. Electroholographic Display Unit
Figures 1(a) and (b) show a photograph and the outline of the electroholographic display unit, respectively. The unit consists of four modules, namely, a universal serial bus (USB) controller, a special-purpose chip (SPC) for holography, an LCD controller, and a reflective LCD panel. We mounted these modules on a printed circuit board of approximately 28cm×13cm in size. The USB controller is used for communication, which is the coordinate datum of 3D objects, between a host computer and the electroholographic display unit. The datum is stored in Static RAM chips (SRAM). SPC automatically starts the computation of a CGH after receiving the datum. SPC implemented by virtual multiple pipeline (VMP) architecture , which is discussed in the next section, can perform the computation of a CGH faster than general-purpose computers, such as personal computers. After finishing the computation, SPC sends the CGH data to a frame buffer of the LCD controller. We adopt SynchronousDRAM chips (SDRAM) as the frame buffer. The LCD controller controls the reflective LCD panel, and the fringe pattern of the CGH is displayed on the reflective LCD panel. When we illuminate a reference light into the reflective LCD panel, we can observe a reconstructed 3D animation.
2.1. Special-Purpose Chip for Holography
We designed a pipeline in SPC by adopting the proposed method, which can calculate the phase on a CGH using two recurrence formulas . Figure 2 shows the outline of the pipeline. The pipeline consists of two modules: the BPU and the CU. We implemented these modules into a field programmable gate array (FPGA) chip. The BPU is used to compute three parameters, θXY,Γ1 and Δ, which are expressed as
where is pre-computed by a host computer.
These parameters are sent to the inputs Γn-1,δn-1 and Δ of the first CU, which computes the following two recurrence formulas and the intensity I(xα+n, yα) on a CGH:
where the parameter n, which is normalized by p, indicates a coordinate on a CGH. The cascade connection of CUs, as shown in Fig. 2, can compute the two recurrence formulas of Eq. (3) and the intensity I(xα+n, yα) of Eq. (4).
We developed a handmade electroholographic display unit. In the handmade unit, we implemented one BPU and 26 CUs into a FPGA chip (EP20K300EQC240-1X, ALTERA Corporation). The gate number of the FPGA chip was equivalent to approximately 300,000 gates. The handmade unit could calculate 27 intensities on a CGH in parallel at one clock cycle of 35 MHz. The clock frequency for the FPGA chip was limited to a clock cycle of 35 MHz for the following two reasons. First, the handmade unit was a handmade electronic circuit. Second, we implemented an LCD controller along with one BPU and 26 CUs in the same FPGA chip.
We designed and developed the new electroholographic display unit shown in Fig. 1 in order to address these problems. We developed the unit on a printed circuit board, and separated the computational modules (BPU and CUs) and the LCD controller into two FPGA chips. Thus, electronically, the unit is faster than the handmade unit. For the computational modules, we adopted an FPGA chip (EP20K300EQC240-1X, ALTERA Corporation). As memory chips for storing 3D object information, we adopted asynchronous SRAM chips because we could lower the degree of difficulty for the electronic circuit design.
Furthermore, in order to improve the computational performance of the handmade unit, we redesigned the pipeline of the new unit to have VMP architecture. The CU has the computational circuit shown by Eq. (4), which is referred to as the intensity unit (IU). The IU of the handmade unit is shown in Fig. 3(a). In the figure, the symbols “COS”, “DFF”, and “ACC” denote the look-up table for computing the cosine function, the D flip-flop, and the accumulator, respectively. The IU of the handmade unit could compute one intensity I(xα+n, yα) of Eq. (4) at one clock cycle of 35 MHz.
The IU of the new unit is shown in Fig. 3(b). In this figure, the symbols “DFF1” and “DFF2” denote D flip-flop 1 and D flip-flop 2. The symbol “Selector” denotes the circuit that selects the outputs of “DFF1” and “DFF2” by the vp_sw signal. In the new unit, the clock frequency for reading 3D object information from the SRAM chips is 40 MHz. In addition, we used a phase-locked loop (PLL) in the FPGA chip to generate a 80-MHz clock signal from the 40-MHz clock signal. The 80-MHz clock signal is supplied to circuits in the BPU and the CUs. During the computation of a CGH, the vp-sw signal is periodically toggled between 1 and 0 at 40 MHz.
The parameters x j, yj and Pj are supplied to the BPU from the SRAM chips at 40 MHz. In Fig. 2, coordinates (xα, yα) and (xα+CN,yα) are automatically set on registers in the FPGA chips so that they can be switched quickly. Here, CN is the total number of CUs in the FPGA chip. The two coordinates are alternately supplied to the BPU at 80 MHz. Therefore, we can calculate Eq. (2), Eq. (3) and the cosine function in Eq. (4) alternately for the two coordinates at 80 MHz. The IU of the new unit can calculate the intensities I(xα,yα) and I(xα+CN,yα) at 40 MHz because the output of the look-up table for the cosine function is selected and accumulated by “Selector” and “ACC” by the vp_sw signal
Thus, we can compute the two intensities by simply adding the selector and one DFF to the IU of the handmade unit. This technique has an advantage with respect to hardware cost because the calculation speed of the new unit is twice as fast as the old unit, without doubling the number of CUs. A pipeline implemented by the above method is referred to as VMP architecture. The SPC can compute 60 intensities on a CGH at one clock cycle of 40 MHz because we implemented one BPU and 30 CUs with VMP (CN=30) into SPC.
We used an FT8U245AM manufactured by the FTDI Corporation as a USB controller. The communication speed of the controller was approximately 53 KByte/s. In Fig. 1(b), the communication time from a host computer to the SRAM chips for a 3D object consisting of approximately 400 points is approximately 0.06 seconds. The computation time by the SPC for computing a CGH of size 800×600 from the 3D object is approximately 0.08s. The communication time for the CGH data from the SPC to the LCD controller is approximately 0.012 seconds. Therefore, the total time, i.e., the sum of the communication times and the computation time, is approximately 0.15 seconds.
2.2. Optical system and experimental result
We implemented the LCD controller on a FPGA chip (EP1K100QC208-1, ALTERA Corporation), which is equivalent to approximately 100,000 gates. The chip was activated at 60 MHz. The reflective LCD has a resolution of 800×600, a pixel pitch of 12µm, an active area of 9.6mm×7.2mm, and a maximum refresh rate of 360 Hz.
Figure 4 shows the outline of an optical system with the display unit. In the figure, a light emitting diodes (LED) is used as the reference light for the CGH, the combination of a pinhole and lens L1 are used to form the plane wave of the reference light. The beam splitter leads the plane wave to the reflective LCD and leads light diffracted by the reflective LCD to lens L2. L2 and L3 are convex lenses. L2 is used to shorten the viewing distance of a reconstructed 3D object, and L3 is used to expand the viewing size of the reconstructed 3D object.
We can obtain a CGH of 800×600 grids in size from a 3D object consisting of approximately 400 points in approximately 0.15 seconds by the display unit, i.e., approximately 7 CGHs per second. An observer can perform operations, such as rotation and movement, to reconstructed 3D objects by use of a keyboard, while viewing the reconstructed 3D object. Figures 5 and 6 show examples of observer operations on reconstructed 3D animations.
We developed an electroholographic display unit with the special-purpose chip for holography and a reflective LCD panel. Using the newly developed display unit, we could obtain a reconstructed 3D animation faster than by using current personal computers. However, the viewing zone of a reconstructed 3D animation from the unit was narrow because the diffracted angle from the reflective LCD panel with 12µm pixel pitch was approximately 3° for the wavelength of 500~700nm. A well-known method for expanding the viewing zone of an electroholographic display is to enlarge the display area of a CGH. We can easily add multiple units to the optical system because we have implemented the unit on a small printed circuit board. In future studies, we are planning to develop a large-scale real-time electroholographic display system with the 16 units in order to enlarge the viewing zone. The applications of this system will include the visualization of numerical simulations, entertainment, medical imagery, and computer aided design.
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