We developed a one-unit system for electroholography, which consists of a special-purpose computational chip and a high-resolution, reflective mode, liquid-crystal display panel as a spatial light modulator. We implemented them on one board whose size is approximately 20 cm × 20 cm. The chip makes a computer-generated hologram whose size is 800 × 600 at nearly real time (~0.5 s) for an object consisting of 1000 points. The pixel pitch of the display panel is 12 μm, and the resolution is 800 × 600. It reconstructs a three-dimensional motion image whose size is approximately 3 cm × 3 cm × 3 cm. The system can be readily scaled up, since the units consisting of the chip and the display are easily set in parallel.
©2004 Optical Society of America
A real-time electroholography system [1–3] by computer-generated hologram (CGH)  is said to be an ultimate three-dimensional (3-D) television because holography is the only technology that can directly record and reconstruct a 3-D image. It is, however, difficult to develop the system into practical use, since electroholography has two difficulties . One is a spatial light modulator (SLM) that is minute enough to display a minute fringe pattern of hologram. In holography, an image is reconstructed with a diffracted light. For a satisfactory range of diffraction, therefore, a SLM needs to have a fine, minute pixel pitch—ideally, a visible light wavelength of ~1 μm. At present, unfortunately, we have no electronic display device whose pixel pitch is ~1 μm. Recently, however, the resolution of reflective-mode display devices, such as the reflective liquid-crystal display (LCD) or the digital micromirror device (DMD), has become increasingly higher. For the LCD, a less than 10-μm pixel pitch panel debuted on the market. A relatively good reconstruction as a SLM by use of a reflective LCD or a DMD has been reported [6, 7]. In our one-unit system, we adopted a reflective LCD that has a pixel pitch of 12 μm and a resolution of 800 × 600.
Another difficulty is achieving the high-performance computational power that is required for generating holograms at video rate of ~30 frames/s. In holography, the cost of data processing is proportional to M ×N, where M is the number of points of a 3-D object and N is the number of points of a hologram (the display resolution). On the other hand, the cost in a two-dimensional (2-D) display system is proportional only to the display resolution. Moreover, since a display for a hologram requires high spatial resolution, the number of pixels inevitably increases. In practical use, for example, even if we develop such an ideal display as a 10 cm × 10 cm hologram with a pixel pitch of 1 μm, the number of pixels will still be 1010 and would require a computational power that is 106 times faster than today’s computers.
Some researchers developed the fast algorithms for CGH [8–10], which calculated CGH more than 10 times faster than the direct-calculation algorithm. Even by the fastest algorithms, a personal computer (PC) with a 3.2-GHz Pentium 4 CPU requires 2 s per CGH, for example, for M = 1000 and N = 800 × 600. As another approach, we have studied the special-purpose hardware system for holography [11–15]. Since data on a hologram can be calculated in parallel, if we can implement the calculation circuits for CGH massively in integrated circuit (IC), the calculation accelerates in proportion to the number of circuits. In our one-unit system, we adopted a middle-scale (3×105 gates) rewritable field programmable gate array (FPGA) chip. The special-purpose chip calculates the intensities of 27 points on CGH in parallel.
In this paper, we report a one-unit system consisting of a special-purpose computational chip and a reflective LCD panel, which we developed toward a 3-D television system. In Section 2, we describe the special-purpose computational chip. In Section 3, we describe the optical setup and our one-unit system. We also show an example of the reconstruction. In Section 4, we discuss future plans, such as the parallel system.
2. Special-purpose calculation chip for CGH
In this section, we briefly describe a numerical procedure used in our special-purpose chip. Since the pixel pitch of LCD is roughly 12 μm, the diffracted angle is narrow at ~3°. Therefore, we adopt the algorithm of the in-line hologram. Namely, a plane-wave reference light is incident perpendicularly on a hologram. In that case, the calculation of CGH is a simple arithmetic operation as follows:
Here, the indices α and j show the hologram and the object respectively, Aj is the intensity of the object, λ is the wavelength of the reference light, xα and yα are the horizontal and vertical components of a grid on the hologram, and xj, yj, and zj are the horizontal, vertical, and depth components of a grid on the virtual object. For x ,y«z, Eq. (1) can be approximated as the following expression by Fresnel approximation:
Here, we replace (xα - xj) and (yα - yj) with xα j and yα j. Normalizing the parameters of the positions on Eq. (2) by the pixel pitch of hologram p we obtain the next equation:
Here, X, Y, and Z are integers. Using Eq. (3), we can calculate CGH with recurrence formulas by additions. We show the schematic drawing in Fig. 1 and the equations as follows. First, we calculate the intensity I(Xα,Yα) at one point on the hologram by using Θ0, namely, 5), directly. Next, for the points on the horizontal (x-axis direction) line, we can calculate them by using Eq. (6), namely, by additions only. For the next line, we replace Yα with Yα+1 and calculate them with the same procedure (for details, see Refs.  and ).
The significant feature of this algorithm is that it requires only two multiplications, which is a large advantage for hardware design. This is because a multiplier occupies a large area of circuits. Compared with the circuits implemented by Eq. (3), directly, this algorithm reduces the circuits’ size by five times. Using this algorithm, we implemented one unit of Eq. (5) and 26 units of Eq. (6) by use of a pipeline architecture into a middle scale (approximately 3×105 gates) FPGA, EP20K300E by ALTERA Corporation. Therefore, the special-purpose chip calculates 27 intensities on CGH in parallel at one clock cycle. The clock cycle of the chip is low speed at 35 MHz because the system is a hand-made prototype machine. However, the chip is four times faster than the latest PC. For a 3-D object consisting of 1000 points, the chip makes one 800 × 600 sheet of CGH in 0.5 s, whereas a PC with a 3.2-GHz Pentium 4 CPU and 2 Gbytes of memory does it in 2 s. Note that with the direct calculation algorithm of Eq. (1), such a PC produces the CGH in 60 s.
The speed, 0.5 s, in our prototype system is not yet a real-time motion reconstruction. For a higher quantity of object data, for example, M = 10,000, the calculation time increases to 5 s per CGH. However, this is not an essential problem. For the real-time reconstruction, we can solve the problem by using a FPGA with a scale that is ten times larger and by activating the chip at a clock frequency that is ten times. Both are available with today’s technology.
3. One-unit system board for electroholography
Figure 2 displays our optical setup for electroholography, which includes a PC, random access memory (RAM), and a special-purpose chip, which was mentioned in Section 2 as the calculation system for CGH. In the figure, RAM is the memory for storing object data sent from the host PC. The object data are converted to the hologram data by the special-purpose computational chip and are sent to the LCD panel directly. We used a light-emitting diode (LED) as the reference light source. The reference light from the LED is collimated by the lens and incident to the LCD with use of the beam splitter. A LED has the advantages of small size, low cost, and safety in comparison with a laser. It was confirmed that we could use a LED as a reference light for electroholography . In this system, we can observe a conjugate image by CGH through the LCD directly or a real image through the output lens placed at the point where the real image is focused.
For the one-unit system we mounted all parts in Fig. 2, except the PC, on one board whose size was approximately 20 cm × 20 cm, as shown in Fig. 3. The LCD panel used here is CMD8X6D, made by Colorado Microdisplay Corporation. The resolution is 800 × 600 with a pixel pitch of 12 μm. We also designed the LCD controller and implemented it into the same FPGA chip that we implemented in the CGH calculation circuits. We adopted a universal serial bus (USB) as the interface between the one-unit system board and PC, since USB is a standard interface, also compatible with notebook-type PCs, and has enough speed for our system. We completed the manual assembly of the prototype system in February 2003.
We show a reconstructed example from this system in Fig. 4, which is a real image of CGH. Here, we set 1 m from the LCD panel (hologram) as the reconstruction area where the real image was focused. Since the diffracted angle by 12 μm pixel pitch is ~3° for the wavelength of 500–700 nm (visible light range), the distance of 1 m provides ~ 3 cm reconstruction area. The original graphic of the teapot in Fig. 4 was made with 3-D graphic software on a PC and was constructed with 3000 points. We used a red LED as the reference light and captured the image with a digital camera.
4. Parallel system by the one-unit system
As shown in Fig. 4, a reflective LCD panel can reconstruct relatively clear 3-D images. However, the viewing zone, depending on the diffracted light angle, is still small. Since the distance between our two eyes is ~6.5 cm, the observation with both eyes in relatively wide range requires less than 5-μm pixel pitch. The pixel pitch of 5 μm produces ~7° of diffracted light angle and can produce a reconstructed image greater 10 cm. A LCD panel with a 5-μm pixel pitch will be produced in the near future; pixel pitch is getting shorter every year. However, the panel size with 5-μm pixel pitch is very small, for example, 5 mm ×5 mm for the resolution of 1000 ×1000. For the practical use of electroholography, therefore, we need to parallelize display panels. The increase of panels, of course, causes the increase of calculation cost.
For overcoming such a problem, the system comprising special-purpose computational chips combined with display panels is effective, since it can be easily parallelized and expanded. It has two advantages: First, we can operate with distributed parallel processing, including data flow. Second, we can easily scale up the system. We show a parallel processing system in Fig. 5. Data flow along the directions of the arrows. Note, especially, that a host computer sends only object data. Even for 100,000 points of object data, the present day’s communication speed of ~100 Mbyte/s is enough. Referring to the object data stored in RAM simultaneously, each calculation chip converts them to hologram data for each LCD panel. The calculations are independently executed in parallel. No bottlenecks of data communication occur. If we expand the display area, we add the unit consisting of the special-purpose computational chip and the LCD panel. It seems that this system would be effective for practical application of electroholography.
To verify the efficiency of such a parallel system, we are developing a printed circuit board (PCB) of our system (Fig. 3) as shown in Fig. 6 and are making several boards as part of our next study. In the PCB, we divide the CGH calculation circuits and the LCD control circuits between two chips, since the PCB has the larger capacity for chips. Although it is now under verification, the calculation chip can have one unit of Eq. (5) and 38 units of Eq. (6), namely, 39 parallel processing units, and it can operate at 80 MHz. We are going to construct a parallel system and hope that we can report favorable results in the near future.
This research was partly supported by Grant-in-Aid for Scientific Research (C) (14550035).
References and links
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