In this paper, we present a scheme for extracting a 10GHz clock from the 80Gb/s optical time division multiplexed (OTDM) return to zero (RZ) data stream. The proposed clock recovery is based on the offset locking technique. By using the input data composed of a repeating “10100000” pattern, residue jitter free operation for clock recovery is demonstrated. The method utilizes a LiNbO3 Mach-Zehnder (MZ) intensity modulator for cross-correlation detections.
© 2004 Optical Society of America
The continuing demand for huge communication bandwidth will fuel the need for higher speed optical transmission systems than those have been installed today. One way to increase the transmission rate is to use OTDM techniques. For OTDM systems, the outputs of each single channel are multiplexed to higher bit rate and transmitted via the optical fiber links. At the receiver end, the received optical OTDM pulse train is demultiplexed into each original channels using various demultiplexing techniques such as nonlinear optical loop mirrors (NOLM)  and semiconductor optical amplifier (SOA) based interferometers . In order to perform the optical demultiplexing function and other OTDM enabling functions like channel add & drop , a stable clock source at the receiver end is needed. This clock is usually generated by some specially designed circuit called clock recovery circuit, which extracts the baseline clock signal from the input data stream. At very high data transmission rates, clock recovery is very difficult to implement by traditional electronic circuits using semiconductor material based transistor technologies. The major difficulty mainly resides in the detection of the cross-correlation between the input data signal and the local clock signal using regular electronic circuits such as double balanced RF mixers.
One approach to overcome this difficulty is the all optical injection mode-locking technique in which the incoming OTDM data signal is injected into the cavity of a laser to be mode-locked. Generally speaking, either a self-pulsating two section laser diode  or a fiber ring laser incorporating SOAs  can be used as the injection-locker. Another approach commonly utilized in this area is the phase locked loop (PLL) type baseline clock extraction technique. In this scheme, a cross-correlator is usually needed to detect the phase difference between the local baseline signal and the input OTDM data signal. By utilizing various SOA based nonlinearities such as cross-gain modulations , or four-wave mixings  as the cross-correlator, successful operations of the PLL type clock recovery have already been demonstrated. Besides the nonlinearity based on the SOAs, one can also employ the nonlinearity (referring to the driving RF signal) based on intensity modulators such as electroabsorption modulator (EAM) or LiNbO3 MZ modulator to realize the cross-correlation functions. Regarding the EAM scheme, it has been reported that by using an EAM as the cross-correlator, clock recovery operation at 80Gb/s can be achieved . Recently, it has also been suggested that self-correlation using EAM can be employed as a powerful tool to characterize the ultra-short optical pulse profiles . Regarding the LiNbO3 MZ modulator scheme, it has been implied that an optical-electrical (OE) oscillator can be constructed with a LiNbO3 MZ modulator as the OE mixer. By injection locking the OE oscillator at 40Gb/s, a prescaled clock at 10GHz has been obtained .
In this paper, we propose to combine the technique of phase-locked loop and the use of a LiNbO3 MZ intensity modulator to construct an OE-PLL type clock recovery unit. The successful operation of the OE-PLL clock recovery is demonstrated by extracting a highly stable residue jitter free 10GHz baseline clock from the 80Gb/s input RZ signal.
2. Principle of operation
The schematic of the proposed PLL circuit is illustrated by Fig. 1. The basic principle of the clock recovery is similar to that of  and can be briefly explained as follows. In order to extract the baseline clock (the 10GHz sub-harmonic from a 80Gb/s input OTDM data stream), the cross-correlation between the locally generated baseline clock and the input OTDM data needs to be carried out. In this work, we use a LiNbO3 MZ intensity modulator to realize this function. To improve the performance of the PLL and help to identify the phase error signal, similar to , offset-locking technique is used. As shown in Fig. 1, Δf is the offset frequency. The offset frequency Δf is chosen to be 2.5MHz in order to center 8Δf around 20MHz which is the center frequency of the band-pass filter used here for 80Gb/s clock recovery. The Δf offset signal is split into two arms. The right arm is frequency multiplied by 8 and is used as the local reference signal while the left arm is sent to the modulation port of a single side band (SSB) modulator. The purpose of the SSB modulator is to modulate the output of a 10GHz VCO signal and produce a sum frequency at 10GHz+Δf. This generated sum frequency signal at 10GHz+Δf is then amplified to high power and applied to the RF modulation port of a 10GHz LiNbO3 MZ intensity modulator. The optical input port of the LiNbO3 MZ intensity modulator takes the 80Gb/s input optical data, and if properly biased at the correct nonlinear region, the modulator will then act as a highly efficient OE mixer. Briefly, although the gating RF signal is modulated at 10GHz+ Δf, due to the strong nonlinearty of the modulator transfer function, there will be a Fourier component at 8(10GHz+Δf) for the gating signal. The 80Gb/s component of the input OTDM signal sees the 8(10GHz+Δf) gate component and produces a 8Δf difference frequency as the beat signal. This beat signal at 8Δf therefore carries the cross-correlation information and is applied to the RF port of a low speed double-balanced phase detector. The LO port of the phase detector takes the 8 Δf reference signal which is previously generated by the frequency doubling processes. The output of the phase detector is filtered out and sent back to the VCO frequency tuning port. This closes the loop. When the loop is closed and the input data rate falls in the locking range, clock recovery can then be achieved.
3. Experimental results
The experimental setup is based on the schematic shown in Fig. 1. For demonstrating clock recovery at 80Gb/s, the input data was chosen to be of the fixed “10100000” pattern. Experimentally, this pattern was realized by gain-switching (GS) a distributed feedback (DFB) diode laser at 10GHz. The pulse width of the GS DFB diode laser was measured to be 20ps and was compressed to 7ps after passing through a segment of 700m dispersion compensating fiber (DCF). The 80Gb/s “10100000” pattern was then obtained by a combination of standard splitting, delaying, and recombining techniques. The optical power of the launched input data was measured to be -2dBm before the LiNbO3 modulator. Since the LiNbO3 modulator is polarization sensitive, in order to optimize the OE down conversion efficiency, a polarization controller was inserted before the modulator input port. The modulator bias was also set to zero since for clock recovery at 80Gb/s, only the even order of the beat signals are needed. The modulator RF driving signal power was 33dBm, which is close to the theoretical optimum value (34dBm) for the RF driving power calculated by expanding the modulator transfer function and maximizing the 8th order down-conversion term. Once the input data stream was launched, by carefully tuning the date transmission rate, successful operation of clock recovery could be recognized if the input data stream could be triggered in a scope by the local clock generated from the VCO. When the system was locked, in Fig. 2, for the ease of comparison, we show together the scope traces of the input data pattern as trigged by the recovered clock and by the original clock, we could see that they are identical. The locking range of this PLL was also measured to be 200kHz.
Since the input data pattern used in our experiment is not a true 80Gb/s signal, there is a possibility that the demonstrated clock recovery might not be really working at 80Gb/s. In order to check that the locking is indeed provided by the cross-correlation between the two 80GHz components (one from the input OTDM data signal, and the other from the modulator gating function), we have measured the RF spectrum of the offset signals at the RF port and LO port of the phase detector respectively. Experimentally, this was done by inserting two splitters before the RF port and LO port of the phase detector when the system was locked. The measured results are shown in Fig. 3, in which two strong 20MHz RF lines (for the LO and RF signal respectively) are clearly visible. Since in the offset-locking technique, the clock recovery is provided by the locking between these two offset 20MHz lines, and the RF port 20MHz offset signal can only be generated through the beating between the two 80GHz components, it then follows that these two 20MHz offset signals are the hard evidence that cross-correlation at 80GHz is the major contributor of the locking mechanism.
To quantify the quality of the recovered clock, an estimation on the jitter performance is important. It is well known that the jitter of the recovered clock is a sum of two parts. The first part (original) comes from the jitter of the input data stream. The second part (residue) comes from the cross-correlation processes and the signal detection processes. Regarding the first part, due to the random nature of individual pulses generated from the amplified spontaneous emission (ASE) seeds in the gain switched operation (white noise process) and the fact that the driving clock signal is also noisy (narrow band noise process), we then have an original jitter in the input data stream. Regarding the second part, if the cross-correlation process is highly effective, the added extra noise could be much smaller than the noise brought in by the input data. Using a linearized phase noise model, one can show that the signal to noise ratio of the phase error detection process could provide a full information on the residue jitter magnitude . The major noise sources involved are: the thermal noise, shot noise, and ASE beat noise if any optical amplifier such as erbium doped fiber amplifier (EDFA) or SOA is used. To estimate the signal to noise ratio, an analysis based on the LiNbO3 modulator transfer function expansions shows that OE down conversion gain of -15dBc is attainable if the RF driving power is close to the optimum value. This -15dBc conversion gain represents a significant improvement when compared with a typical -40dBc conversion gain for the case where FWM in SOA is used as the cross-correlator . Based on the signal to noise ratio analysis, further numerical estimations indicates that the extra residue noise brought in by the -15dBc conversion gain is small, and the jitter of the recovered clock should be dominated by the jitter of the original clock.
To confirm the above conclusion, we have measured the jitter of the recovered clock and that of the original clock using a RF spectrum analyzer. The measured results are shown in Fig. 4 for the recovered clock and the original clock respectively. Note that the RF spectrum of the recovered clock fully resembles that of the original clock. This indicates that during the clock recovery process, no extra noise has been added, and therefore the clock recovery is truly residue jitter free. The measured integrated jitter from 500Hz to 100kHz is 100fs for the recovered clock and 101fs for the original clock respectively.
In conclusion, clock recovery for OTDM has been successfully demonstrated at 80Gb/s by constructing an OE-PLL with a LiNbO3 intensity modulator as the cross-correlator. The estimated jitter for the recovered clock is measured to be 100fs which is shown to be residue jitter free.
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