We present the fabrication of 3D adiabatically tapered structures, for efficient coupling from an optical fiber, or free-space, to a chip. These structures are fabricated integrally with optical waveguides in a silicon-on-insulator wafer. Fabrication involves writing a single grayscale mask in HEBS glass with a high-energy electron beam, ultra-violet grayscale lithography, and inductively coupled plasma etching. We also present the experimentally determined coupling efficiencies of the fabricated tapers using end-fire coupling. The design parameters of the tapered structures are based on electromagnetic simulations and are discussed in this paper.
©2003 Optical Society of America
Optical Integrated Circuits (OICs) have been under development since the 1960’s . As a result, many of the components required to realize OICs have reached a good level of maturity, both theoretically and in terms of their fabrication. At the same time, the transmission characteristics achieved by optical fibers, which in many applications are used to bring light to these circuits, have nearly reached their theoretical limits . However, despite this progress coupling light from an optical fiber into a waveguide within an OIC remains a relatively challenging problem.
To address this, several approaches have been proposed such as: prism couplers , grating couplers , micro-lenses  and tapered optical fibers . The first approach needs hybrid integration between the coupler and the OIC, adding to complexity and cost. The second approach offers good efficiency, but is typically narrow-band. The last two approaches have good efficiency, but have stringent alignment tolerances, thereby leading to high packaging costs. An ideal structure would be one that adiabatically tapers in both the vertical and lateral directions and can be monolithically integrated with the OIC. However, such structures cannot be readily achieved with standard binary lithography techniques.
For this reason many techniques, such as dip-etch process , dynamic etch mask technique , diffusion limited etch , and stepped etching  have been proposed to fabricate vertically tapered structures. All of these methods have disadvantages of either low reproducibility or labor intensive processing. Other techniques, like dry etching using a shadow mask  have been successful in obtaining vertical tapers, but do not necessarily allow for processing on the wafer scale. The review paper by Moerman et al. , explains many such methods to fabricate these structures in III-V materials. Successful fabrication of these structures in polymers was also reported  but these devices have low acceptance in the market due to material reliability concerns.
In this paper, we present the fabrication of tapered structures in silicon-on-insulator wafer, which is well suited for dense wafer-scale integration. Recently, Confluent Photonics Inc. has fabricated such structures by gray tone lithography  and polishing . However, tapers fabricated with the former method are vulnerable to high losses due to misalignment and those fabricated with the latter cannot readily be monolithically integrated within the OIC.
In contrast, our process, which involves ultra-violet, mask-based, grayscale lithography and a subsequent etch process, is amenable to monolithic integration of tapers with the OIC. Alternatively, the substrate with tapered couplers can be further processed to realize other OIC components. Figure 1 shows the steps involved in our process.
In order to ascertain the feasibility of the process and the performance of the resulting devices, we designed a symmetric coupler that consists of an input coupler, a central waveguide section and an output coupler. The cross-sectional variation of the tapers was limited to vertical tapering because of the resolution constraints of the thick resist. Such couplers do not achieve horizontal mode conversion. However this does not limit their applicability, because horizontal mode conversion has been previously demonstrated [15–16]. Furthermore, the tapering geometry was fixed to linear tapers to simplify fabrication, but the developed process can be easily extended to other geometries, such as sinusoidal or quadratic tapers. It should be pointed out that the coupling efficiency is not sacrificed with this choice of geometry, if the taper is sufficiently long . The designed structure is shown in Fig. 2.
Theoretical analysis of symmetric vertical couplers was performed with a 2D beam propagation method (BPM). All simulations were carried out at λ=1.55µm with a 10µm wide Gaussian input beam. The waveguide core, upper cladding and lower cladding materials were taken as Si (n1=3.48), SiO2 (n2=1.5) and air (n3=1), respectively. The input and output facet dimensions were assumed to be h1=10µm, approximately equal to the core diameter of a single mode fiber. Simulations were performed to determine the variation in the coupling efficiency with the taper length (l) of the coupler for the various central waveguide heights (h2), 0.25 and 1µm. The taper length, input facet height and central waveguide height determine the taper angle. The results, summarized in Fig. 3, indicate that coupling efficiency increases with taper length for a given central waveguide height but this increase is not significant for l≥600µm. Therefore, we used a 600µm taper length, which yields greater than 82% efficiency in the design of each of our couplers.
In fabrication, we employ a high-energy beam sensitive (HEBS)  glass mask with UV grayscale lithography. The desired device profile is encoded as an optical density (OD) profile within the mask, after having determined the resist response to varying UV exposure. To pattern the mask blank with a continuous OD profile, we developed a technique that involves deconvolution of the desired OD profile with an experimentally determined electron beam (e-beam) point spread function [19–20]. This scheme works well for patterning devices, which have smooth profiles such as tapered couplers. We used a Raith 50 e-beam lithography tool at 20kV for patterning the mask employed in the fabrication of the tapered couplers. The optical density map of the patterned mask is shown in Fig. 4, along with an overview of the process. After the HEBS grayscale mask is patterned, a single lithographic step is used to transfer the mask pattern into the photoresist. The profile of the photoresist serves as a grayscale etch mask for pattern transfer into the underlying substrate. For the substrate we used a silicon-on-insulator (SOI) wafer that has a 10µm single-crystal Si device layer and buried 1µm SiO2 supported by a 350µm Si handle wafer. The tapers are patterned in the top 10µm layer and the SiO2 underneath acts as the cladding layer for optical confinement.
For the photoresist, we chose AZP4620 because it has low contrast, which is desirable for 3D profiling, and sufficient bleachability. The latter ensures that the exposure penetrates through the thick layer of the resist without excessive absorption in its upper portion. The device profile obtained with HEBS glass grayscale lithography is a function of both optical densities in the mask and the lithography parameters. Gao, et al. modeled this dependence and applied it to grayscale lithography using AZ5214 photoresist . We employed this model to characterize the chosen thick resist and to develop the process for realizing tapered couplers of required dimensions.
Fabrication of tapered couplers involved spinning the resist at low spin speed of 750 rpm to achieve a 12µm film, and a proximity bake with ramp to further prevent resist blistering . After the bake, the resist is exposed with a low intensity intermittent exposure to prevent resist blistering during exposure. The exposed resist was subsequently developed with AZ400 under constant agitation for 3 minutes. Structures realized with this optimized process are shown in the Fig. 5. The couplers are15µm wide and display a certain degree of roundness. We observed that this roundness is lesser for couplers, which tapered only in height in comparison to those, which tapered both in height and width. We also noticed that roundness varies but it can be controlled by further optimization of the mask patterning and lithography process. In particular it should be possible, if desired, to obtain nearly square cross-section in the tapered section. On the other hand, we believe that variation in roundness has little effect on the coupling efficiency. The couplers have input and output facet, each of 10µm high and a central waveguide of 0.25-2µm high depending on the mask design. We were able to get repeatable central waveguide heights within +/- 0.2µm by correct choice of optical density in mask, control of the lithography parameters and careful inspection during the development process.
Following photolithography, we used inductively coupled plasma (ICP) etching to transfer the grayscale pattern in photoresist to the underlying device layer of the SOI wafer. Due to the decoupling between the coil power, which controls the disassociation of reactive species from the bias power, which controls the energy at which the ions strike the sample, ICP etching offers good control of the selectivity between the photoresist etch mask and underlying silicon, while maintaining anisotropy in the etch. These are important features needed for a grayscale etch process. The pattern transfer occurs by the gradual etching away of the resist and exposure to the silicon underneath to the etchant. In this way, the relief height of the etched silicon will be commensurate with the local resist thickness of the etch mask. To ensure a continuous profile and high fidelity in the transfer, we aimed at a 1:1 etch selectivity of resist versus silicon. Furthermore, we employed low pressure and high power ICP process to ensure anisotropy. Specifically, we used SF6 and C4F8 in 1:1 ratio as etch gases at 0.5Pa, 100W bias and 300W ICP power to realize the structures shown in Fig. 6. Finally we diced and polished these devices at their input and output facets in preparation for their experimental characterization.
The experimental setup to characterize these devices was based on end-fire coupling and is schematically shown in Fig. 7. The experiment involved focusing the output of a 1.55µm laser onto the input facet of the tapered structure with a 10X microscope objective and imaging the top surface of the tapered structures with a side-view near IR camera for alignment. We observed the light coupled out of the output facet of the tapered structure with a linear-response 12-bit digital IR camera at 40X magnification and captured the image with a frame grabber. The side-view camera further enables characterization of the scattering loss of the devices. The obtained intensity profiles at the output facets of the symmetric tapers with central waveguide height 0.25, 0.5 and 2µm is shown in Fig. 8. The mode profiles with a single peak suggest that nearly all the energy is concentrated in the fundamental mode except for the coupler with the central waveguide height 0.25µm. The energy coupled out of the device was calculated by summing the intensity of the pixels in the output field. The coupling efficiency of a taper is calculated by taking ratio of the power coupled out from the taper and power coupled out from straight waveguide fabricated concurrently with the taper. For consistency, the input intensity during the measurements was held same, and the number of pixels used in the total power calculation was kept constant. The coupling efficiencies of the tapers calculated in this manner are plotted in Fig. 9. The measured coupling efficiency of 45–60% is lower than the theoretically expected value of 82%, largely due to the scattering losses observed within the central waveguide. We believe that the scattering is due to the experimentally determined 10nm RMS surface roughness of the central waveguides. Presently, we are investigating fabrication and post-fabrication strategies to reduce this roughness; this will likely involve the modification of the etch process or post-fabrication oxidation and wet etch. Although the surface roughness observed with our process is currently on the same scale as that of other processes [13–14], our process in addition to having the potential application to monolithic integration is able to realize devices that taper down to 0.25 µm. We observed that with optimized mask design, good control on lithography parameters and etch parameters the resultant height profiles are reproducible. We are currently working on quantitatively determining the affect of parameter changes on the profile.
To summarize, in this paper we presented a process developed for the fabrication of adiabatic linear tapers for coupling light from free-space or optical fiber to the waveguides of optical integrated circuits. Our process begins with electron beam patterning of a HEBS glass blank. This is then used as a mask for the grayscale exposure of AZ4620 resist. The exposed resist is developed to produce continuous device profiles with a maximum and minimum height of 10 and 0.25µm, respectively. The profiles are then transferred to a device layer of an SOI substrate by dry etching. We have successfully demonstrated efficient coupling between free space and OIC waveguides with the realized structures.
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