M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).

[Crossref]

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.

[Crossref]

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).

[Crossref]

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).

[Crossref]

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).

[Crossref]

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.

[Crossref]

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).

[Crossref]

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).

[Crossref]

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).

[Crossref]

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).

[Crossref]

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).

[Crossref]
[PubMed]

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).

[Crossref]

P. Scheunders, “A genetic Lloyd-max image quantization algorithm,” Pattern Recognit. Lett. 17(5), 547–556 (1996).

[Crossref]

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).

[Crossref]

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).

[Crossref]

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.

[Crossref]

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).

[Crossref]

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).

[Crossref]
[PubMed]

D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.

[Crossref]

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).

[Crossref]

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).

[Crossref]

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).

[Crossref]

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).

[Crossref]

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).

[Crossref]
[PubMed]

P. Scheunders, “A genetic Lloyd-max image quantization algorithm,” Pattern Recognit. Lett. 17(5), 547–556 (1996).

[Crossref]

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.

[Crossref]

C. Brokish and M. Lewis, Texas Instruments Digital Processing Solutions (Texas, 1997), Chap. 2.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.

[Crossref]

Socionext, http://socionextus.com/products/networking-asic/adc-dac/ .

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.

[Crossref]

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.