Abstract

This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

© 2017 Optical Society of America

Full Article  |  PDF Article
OSA Recommended Articles
Silicon photonics manufacturing

William A. Zortman, Douglas C. Trotter, and Michael R. Watts
Opt. Express 18(23) 23598-23607 (2010)

InP photonic circuits using generic integration [Invited]

K. A. Williams, E. A. J. M. Bente, D. Heiss, Y. Jiao, K. Ławniczuk, X. J. M. Leijtens, J. J. G. M. van der Tol, and M. K. Smit
Photon. Res. 3(5) B60-B68 (2015)

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O’s

Philippe P. Absil, Peter Verheyen, Peter De Heyn, Marianna Pantouvaki, Guy Lepage, Jeroen De Coster, and Joris Van Campenhout
Opt. Express 23(7) 9369-9378 (2015)

References

  • View by:
  • |
  • |
  • |

  1. W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
    [Crossref]
  2. L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
    [Crossref]
  3. S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
    [Crossref]
  4. S. K. Selvaraja, “Wafer scale fabrication technology for silicon photonic integrated circuit,” Ph.D. thesis, Ghent University (2011).
  5. W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
    [Crossref] [PubMed]
  6. N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
    [Crossref]
  7. X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
    [Crossref] [PubMed]
  8. L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).
  9. A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).
  10. T.-W. Weng, Z. Zhang, Z. Su, Y. Marzouk, A. Melloni, and L. Daniel, “Uncertainty quantification of silicon photonic devices with correlated and non-gaussian random parameters,” Opt. Express 23, 4242–4254 (2015).
    [Crossref] [PubMed]
  11. D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
    [Crossref]
  12. Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
    [Crossref]
  13. L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
    [Crossref]
  14. Y. Yang, Y. Ma, H. Guan, Y. Liu, S. Danziger, S. Ocheltree, K. Bergman, T. Baehr-Jones, and M. Hochberg, “Phase coherence length in silicon photonic platform,” Opt. Express 23, 16890–16902 (2015).
    [Crossref] [PubMed]
  15. A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.
  16. R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.
  17. L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
    [Crossref]
  18. W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
    [Crossref]
  19. L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
    [Crossref]
  20. N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.
  21. S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.
  22. S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.
  23. X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
    [Crossref] [PubMed]
  24. S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
  25. R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
    [Crossref]
  26. D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
    [Crossref]
  27. https://www.klayout.de
  28. https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK
  29. https://www.lumerical.com
  30. R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
    [Crossref]
  31. Y. Zhang, S. Yang, A. E.-J. Lim, G.-Q. Lo, C. Galland, T. Baehr-Jones, and M. Hochberg, “A compact and low loss y-junction for submicron silicon waveguide,” Opt. Express 21, 1310–1316 (2013).
    [Crossref] [PubMed]
  32. Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
    [Crossref]
  33. Z. Lu, H. Yun, Y. Wang, Z. Chen, F. Zhang, N. A. F. Jaeger, and L. Chrostowski, “Broadband silicon photonic directional coupler using asymmetric-waveguide based phase control,” Opt. Express 23, 3795–3808 (2015).
    [Crossref] [PubMed]

2016 (3)

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

2015 (4)

2014 (5)

Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

2013 (2)

2012 (2)

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
[Crossref] [PubMed]

2011 (1)

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

2010 (2)

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

1997 (1)

R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]

Absil, P.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

Agarwal, A.

A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.

Ayotte, N.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Baehr-Jones, T.

Baets, R.

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Beausoleil, R.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

Beausoleil, R. G.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Bergman, K.

Bienstman, P.

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Blaauw, D.

A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.

Bogaerts, W.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

Bojko, R.

Caverley, M.

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

Chen, C. H.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

Chen, X.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Chen, Z.

Cheng, K. T.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

Chew, W. C.

R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]

Chrostowski, L.

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Z. Lu, H. Yun, Y. Wang, Z. Chen, F. Zhang, N. A. F. Jaeger, and L. Chrostowski, “Broadband silicon photonic directional coupler using asymmetric-waveguide based phase control,” Opt. Express 23, 3795–3808 (2015).
[Crossref] [PubMed]

Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]

X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
[Crossref] [PubMed]

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
[Crossref]

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

Claes, T.

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Cone, C.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Daniel, L.

Danziger, S.

Delvaux, C.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Dhaene, T.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Dumon, P.

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Eid, N.

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

Faraon, A.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Fard, S. T.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

Fattal, D.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Ferguson, J.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Fernandez, L.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

Fiers, M.

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

Fiorentino, M.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Flückiger, J.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Flueckiger, J.

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

Galland, C.

Grist, S.

Guan, H.

Hautala, J.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

Heyn, P. De

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Hochberg, M.

Hsu, E. Y.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Huang, T. C.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

Jaeger, N. A. F.

Jayatilleka, H.

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

Jhoja, J.

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Keyvaninia, S.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Kim, C.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Klein, J.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Kumar Selvaraja, S.

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

LaRochelle, S.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Lavagno, L.

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

Lepage, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Li, A.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Li, S.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Li, Z.

Lim, A. E.-J.

Liu, A.

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Liu, Y.

Lo, G.-Q.

Locorotondo, S.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Lu, Z.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Z. Lu, H. Yun, Y. Wang, Z. Chen, F. Zhang, N. A. F. Jaeger, and L. Chrostowski, “Broadband silicon photonic directional coupler using asymmetric-waveguide based phase control,” Opt. Express 23, 3795–3808 (2015).
[Crossref] [PubMed]

Ma, Y.

Martin, G.

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

Marzouk, Y.

Mashanovich, G. Z.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Melati, D.

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Melloni, A.

Mickelson, A. R.

Milenin, A.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Mohamed, M.

Morichetti, F.

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Murdoch, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Nedeljkovic, M.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Ocheltree, S.

Ong, P.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Pathak, S.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Peng, Z.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Pond, J.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Reed, G. T.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Rosseel, E.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

Santori, C.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Scheffer, L.

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

Schmid, J. H.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Sedra, A. S.

A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).

Selvaraja, S. K.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

S. K. Selvaraja, “Wafer scale fabrication technology for silicon photonic integrated circuit,” Ph.D. thesis, Ghent University (2011).

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

Shang, L.

Shekhar, S.

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

Shi, W.

Simard, A. D.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Smith, K. C.

A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).

Song, J.

R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]

Spina, D.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Sterckx, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Su, Z.

Tabat, M.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

Tai, W.

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Thomson, D. J.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Thourhout, D. V.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Trotter, D. C.

Van Campenhout, J.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Van Thourhout, D.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Van Vaerenbergh, T.

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Vos, K. De

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Wagner, R. L.

R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]

Wang, X.

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]

X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
[Crossref] [PubMed]

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

Wang, Y.

Watts, M. R.

Weng, T.-W.

Winroth, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Wu, R.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

Wu, Y.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

Xie, W.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

Xing, Y.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Xu, D. X.

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

Yang, S.

Yang, Y.

Yun, H.

Zhang, F.

Zhang, Y.

Zhang, Z.

Zolotov, V.

A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.

Zortman, W. A.

Adv. Opt. Photonics (1)

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Appl. Opt. (1)

IEEE J. Sel. Top. Quantum Electron. (3)

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

IEEE Photonics Technol. Lett. (1)

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

IEEE Trans. Antennas Prop. (1)

R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]

Laser Photonics Rev. (1)

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

Opt. Express (7)

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

T.-W. Weng, Z. Zhang, Z. Su, Y. Marzouk, A. Melloni, and L. Daniel, “Uncertainty quantification of silicon photonic devices with correlated and non-gaussian random parameters,” Opt. Express 23, 4242–4254 (2015).
[Crossref] [PubMed]

X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
[Crossref] [PubMed]

Y. Zhang, S. Yang, A. E.-J. Lim, G.-Q. Lo, C. Galland, T. Baehr-Jones, and M. Hochberg, “A compact and low loss y-junction for submicron silicon waveguide,” Opt. Express 21, 1310–1316 (2013).
[Crossref] [PubMed]

Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]

Z. Lu, H. Yun, Y. Wang, Z. Chen, F. Zhang, N. A. F. Jaeger, and L. Chrostowski, “Broadband silicon photonic directional coupler using asymmetric-waveguide based phase control,” Opt. Express 23, 3795–3808 (2015).
[Crossref] [PubMed]

Y. Yang, Y. Ma, H. Guan, Y. Liu, S. Danziger, S. Ocheltree, K. Bergman, T. Baehr-Jones, and M. Hochberg, “Phase coherence length in silicon photonic platform,” Opt. Express 23, 16890–16902 (2015).
[Crossref] [PubMed]

Photonics Res. (1)

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Proc. SPIE (4)

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

Other (13)

A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

https://www.klayout.de

https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK

https://www.lumerical.com

S. K. Selvaraja, “Wafer scale fabrication technology for silicon photonic integrated circuit,” Ph.D. thesis, Ghent University (2011).

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
[Crossref]

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

Cited By

OSA participates in Crossref's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.

Alert me when this article is cited.


Figures (23)

Fig. 1
Fig. 1 Proposed circuit simulation approach. First, the designer generates a layout and uses the netlist extraction tool to transfer the layout to a circuit simulator. Second, wafer-scale correlated variations are automatically simulated based on the characterized results from fabrication, and variations at each component position are assigned to the component. Then, the optical response of each component will automatically get updated according to obtained variations. Finally, circuit simulation is performed. Results include both common mode and differential mode variability.
Fig. 2
Fig. 2 (a) Cross-section schematic of an SOI strip waveguide; (b) effective index of strip waveguides for various waveguide widths; (c) effective index of strip waveguides for various waveguide heights.
Fig. 3
Fig. 3 (a) Schematic layout of the racetrack resonator test device; (b) transmission spectrum for such a device without fabrication variations. FSR is free-spectral-range.
Fig. 4
Fig. 4 Simulation results for racetrack resonators with a nominal waveguide height of 220 nm and various waveguide widths. (a) Transmission spectra; (b) group indices at resonances; (c) resonance wavelength versus waveguide width for a selected resonance mode; (d) group index versus waveguide width for a selected resonance mode.
Fig. 5
Fig. 5 Simulation results for racetrack resonators with a nominal waveguide width of 500 nm and various waveguide heights. (a) Transmission spectra; (b) group indices at resonances; (c) resonance wavelength versus waveguide height for a selected resonance mode; (d) group index versus waveguide height for a selected resonance mode.
Fig. 6
Fig. 6 Error test results in a Δw deviation range of ±20 nm and a Δh deviation range of ±10 nm, for the proposed variability characterization method. (a) Width extraction error; (b) height extraction error.
Fig. 7
Fig. 7 (a) Schematic layout for the fabricated racetrack resonator; (b) distribution of racetrack resonators on each wafer die; (c) wafer map for the fabricated multi-project-wafer.
Fig. 8
Fig. 8 Characterization results for the manufacturing variability a 200-mm-wafer. (a) Measured spectra for the 61 devices on die #20; (b) extracted ng for the 61 devices on die #20; (c) extracted Δw versus position on die #20; (d) extracted Δh versus position on die #20; (e) extracted ng versus λres for the 2074 devices on the wafer; (f) histogram for extracted Δw across the wafer; (g) histogram for extracted Δh across the wafer.
Fig. 9
Fig. 9 (a) Flow chart for the enhanced Monte Carlo methodology; (b) simulated virtual wafer for waveguide width deviations; (c) simulated virtual wafer for waveguide height deviations.
Fig. 10
Fig. 10 An example circuit consisting of two grating couplers connected by a waveguide. (a) Physical layout; (b) simulation schematic in the circuit simulator.
Fig. 11
Fig. 11 Illustration for the die selection and variation mapping of within-wafer analysis.
Fig. 12
Fig. 12 Illustration for the manufacturing variation simulations of wafer-to-wafer analysis.
Fig. 13
Fig. 13 (a) A 100 mm × 100 mm random distribution map z(x, y) generated with σ = 2; (b) a Gaussian filter map g(x, y) generated with l = 4 mm; (c) the correlated variation wafer map m(x, y).
Fig. 14
Fig. 14 (a) A 100 mm × 100 mm correlated variation wafer map m(x, y), which is simulated using a coarse simulation mesh; (b) and (c) are the variation maps for a 10 mm × 10 mm die located at the top right corner of the wafer before and after interpolation, respectively.
Fig. 15
Fig. 15 Diagram for Δw and Δh averaging in the waveguide compact model.
Fig. 16
Fig. 16 S-parameter component model. (a) Process corners for two process parameters: waveguide width variation, Δw, and height variation, Δh; (b) S-parameters for the nominal design, four process corners, and one interpolated geometry of a 2×2 splitter.
Fig. 17
Fig. 17 Layout decomposition examples of ring resonators. (a) All-pass ring resonator; (b) add-drop ring resonator.
Fig. 18
Fig. 18 A ring resonator based single-channel photonic filter circuit. (a) Physical layout; (b) circuit simulation schematic.
Fig. 19
Fig. 19 Simulation results for a ring resonator based single-channel filter. (a) ideal transmission spectrum; (b) transmission spectra on 3 representative dies with fabrication variations; (c) extracted group index versus resonance wavelength for the filter in 1600 simulations; (d) and (e) are histograms of resonance wavelengths and extinction ratios for the filter in 1600 simulations, respectively.
Fig. 20
Fig. 20 A photonic ring resonator based dual-channel filter circuit. (a) Physical layout; (b) circuit simulation schematic.
Fig. 21
Fig. 21 Simulation results for the ring resonator based dual-channel filter. (a) Output transmission spectra without fabrication variation; (b) and (c), respectively, are histograms for resonance wavelengths λres and channel spacings Δλ of the filter in 1600 simulations.
Fig. 22
Fig. 22 Histograms for the channel spacings for filter designs with d=30 μm, d=150 μm, and d=300 μm.
Fig. 23
Fig. 23 An example Mach-Zehnder interferometer circuit. (a) Circuit layout; (b) local pattern density for the Si layer of the layout, which is calculated using a 6 μm × 6 μm sampling window with a scanning step of 0.3 μm.

Tables (7)

Tables Icon

Table 1 Statistical results for the manufacturing variations of a 200-mm-wafer fabricated through a 248-nm DUV lithography process

Tables Icon

Table 2 Literature results for wafer-to-wafer fabrication variations

Tables Icon

Table 3 Literature results for within-wafer fabrication variations

Tables Icon

Table 4 Input parameters for the virtual wafer model

Tables Icon

Table 5 Monte Carlo analysis results for the ring resonator based single-channel filter

Tables Icon

Table 6 Monte Carlo analysis results for a dual-channel filter design with d=30 μm.

Tables Icon

Table 7 Monte Carlo analysis results for various dual-channel filters designs

Equations (16)

Equations on this page are rendered with MathJax. Learn more.

E t h r u E i n = e i ( π + 2 π λ n e f f L ) a t e i 2 π λ n e f f L 1 t a e i 2 π λ n e f f L
n g = λ r e s 2 F S R L
[ Δ n g Δ λ r e s ] = [ n g w n g h λ r e s w λ r e s h ] [ Δ w Δ h ]
[ Δ w Δ h ] = [ n g w n g h λ r e s w λ r e s h ] 1 [ Δ n g Δ λ r e s ]
λ r e s w = 0.585911 ( n m / n m )
n g w = 0.001650 ( / n m )
λ r e s h = 1.36330 ( n m / n m )
n g h = 0.001091 ( / n m )
E r r o r Δ w = | Δ w g i v e n Δ w e x t r a c t e d | ; E r r o r Δ h = | Δ h g i v e n Δ h e x t r a c t e d |
g ( x , y ) = 1 π l 2 e ( x 2 l 2 / 2 + y 2 l 2 / 2 )
m ( x , y ) = [ [ g ( x , y ) ] [ z ( x , y ) ] ]
m ( x , y ) = [ [ g ( x , y ) ] [ z ( x , y ) ] ] + c
n e f f ( λ ) = n e f f ( λ 0 ) + ( λ λ 0 ) d n e f f d λ | λ = λ 0 + ( λ λ 0 )   2 d 2 n e f f d λ 2 | λ = λ 0
n g ( λ 0 ) = n e f f ( λ 0 ) λ 0 d n e f f d λ |   λ = λ 0
D ( λ 0 ) = λ 0 c d 2 n e f f d λ 2 |   λ = λ 0
w a v g = w 0 + 1 N n = 1 N Δ w n , h a v g = h 0 + 1 N n = 1 N h n

Metrics