Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability

Zeqin Lu; Jaspreet Jhoja; Jackson Klein; Xu Wang; Amy Liu; Jonas Flueckiger; James Pond; Lukas Chrostowski

doi:10.1364/OE.25.009712

Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability

Zeqin Lu, Jaspreet Jhoja, Jackson Klein, Xu Wang, Amy Liu, Jonas Flueckiger, James Pond, and Lukas Chrostowski

Optics Express
Vol. 25,
Issue 9,
pp. 9712-9733
(2017)
•https://doi.org/10.1364/OE.25.009712

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Zeqin Lu, Jaspreet Jhoja, Jackson Klein, Xu Wang, Amy Liu, Jonas Flueckiger, James Pond, and Lukas Chrostowski, "Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability," Opt. Express 25, 9712-9733 (2017)

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Related Topics
Table of Contents Category
- Integrated Optics
Optics & Photonics Topics
?

The topics in this list come from the OSA Optics and Photonics Topics applied to this article.
Previously assigned OCIS codes
- Probability theory, stochastic processes, and statistics (000.5490)
- Integrated optics devices (130.3120)
- Waveguides (230.7370)

About this Article
History
- Original Manuscript: February 13, 2017
- Revised Manuscript: March 29, 2017
- Manuscript Accepted: March 30, 2017
- Published: April 19, 2017

Accessible

Open Access

Abstract

This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

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References

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Year
|
Author
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Publication

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]
L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]
S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]
S. K. Selvaraja, “Wafer scale fabrication technology for silicon photonic integrated circuit,” Ph.D. thesis, Ghent University (2011).
W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]
N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]
X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
[Crossref] [PubMed]
L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).
A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).
T.-W. Weng, Z. Zhang, Z. Su, Y. Marzouk, A. Melloni, and L. Daniel, “Uncertainty quantification of silicon photonic devices with correlated and non-gaussian random parameters,” Opt. Express 23, 4242–4254 (2015).
[Crossref] [PubMed]
D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]
Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]
L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]
Y. Yang, Y. Ma, H. Guan, Y. Liu, S. Danziger, S. Ocheltree, K. Bergman, T. Baehr-Jones, and M. Hochberg, “Phase coherence length in silicon photonic platform,” Opt. Express 23, 16890–16902 (2015).
[Crossref] [PubMed]
A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.
R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.
L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]
W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]
L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
[Crossref]
N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.
S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.
S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.
X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]
S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]
D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]
https://www.klayout.de
https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK
https://www.lumerical.com
R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]
Y. Zhang, S. Yang, A. E.-J. Lim, G.-Q. Lo, C. Galland, T. Baehr-Jones, and M. Hochberg, “A compact and low loss y-junction for submicron silicon waveguide,” Opt. Express 21, 1310–1316 (2013).
[Crossref] [PubMed]
Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]
Z. Lu, H. Yun, Y. Wang, Z. Chen, F. Zhang, N. A. F. Jaeger, and L. Chrostowski, “Broadband silicon photonic directional coupler using asymmetric-waveguide based phase control,” Opt. Express 23, 3795–3808 (2015).
[Crossref] [PubMed]

2016 (3)

L. Chrostowski, Z. Lu, J. Flückiger, J. Pond, J. Klein, X. Wang, S. Li, W. Tai, E. Y. Hsu, C. Kim, J. Ferguson, and C. Cone, “Schematic driven silicon photonics design,” Proc. SPIE 9751, 975103 (2016).
[Crossref]

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

L. Chrostowski, Z. Lu, J. Flueckiger, X. Wang, J. Klein, A. Liu, J. Jhoja, and J. Pond, “Design and simulation of silicon photonic schematics and layouts,” Proc. SPIE 9891, 989114 (2016).
[Crossref]

2015 (4)

Y. Yang, Y. Ma, H. Guan, Y. Liu, S. Danziger, S. Ocheltree, K. Bergman, T. Baehr-Jones, and M. Hochberg, “Phase coherence length in silicon photonic platform,” Opt. Express 23, 16890–16902 (2015).
[Crossref] [PubMed]

T.-W. Weng, Z. Zhang, Z. Su, Y. Marzouk, A. Melloni, and L. Daniel, “Uncertainty quantification of silicon photonic devices with correlated and non-gaussian random parameters,” Opt. Express 23, 4242–4254 (2015).
[Crossref] [PubMed]

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Z. Lu, H. Yun, Y. Wang, Z. Chen, F. Zhang, N. A. F. Jaeger, and L. Chrostowski, “Broadband silicon photonic directional coupler using asymmetric-waveguide based phase control,” Opt. Express 23, 3795–3808 (2015).
[Crossref] [PubMed]

2014 (5)

Y. Wang, X. Wang, J. Flueckiger, H. Yun, W. Shi, R. Bojko, N. A. F. Jaeger, and L. Chrostowski, “Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits,” Opt. Express 22, 20652–20662 (2014).
[Crossref]

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).

D. X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. V. Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform–have we found the sweet spot,” IEEE J. Sel. Top. Quantum Electron. 20, 189–205 (2014).
[Crossref]

2013 (2)

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Y. Zhang, S. Yang, A. E.-J. Lim, G.-Q. Lo, C. Galland, T. Baehr-Jones, and M. Hochberg, “A compact and low loss y-junction for submicron silicon waveguide,” Opt. Express 21, 1310–1316 (2013).
[Crossref] [PubMed]

2012 (2)

W. Bogaerts, P. De Heyn, T. Van Vaerenbergh, K. De Vos, S. Kumar Selvaraja, T. Claes, P. Dumon, P. Bienstman, D. Van Thourhout, and R. Baets, “Silicon microring resonators,” Laser Photonics Rev. 6, 47–73 (2012).
[Crossref]

X. Wang, W. Shi, H. Yun, S. Grist, N. A. F. Jaeger, and L. Chrostowski, “Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process,” Opt. Express 20, 15547–15558 (2012).
[Crossref] [PubMed]

2011 (1)

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

2010 (2)

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

1997 (1)

R. L. Wagner, J. Song, and W. C. Chew, “Monte Carlo simulation of electromagnetic scattering from two-dimensional random rough surfaces,” IEEE Trans. Antennas Prop. 45, 235–245 (1997).
[Crossref]

Absil, P.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in 8th IEEE International Conference on Group IV Photonics (2011), pp. 71–73.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using wafer-scale corrective etching for silicon nano-photonic device,” in Proceedings of the 2011 Annual Symposium of the IEEE Photonics Benelux Chapter (2011), pp. 289–292.

Agarwal, A.

A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in International Conference on Computer Aided Design (2003), pp. 900–907.

Ayotte, N.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Baehr-Jones, T.

Baets, R.

Beausoleil, R.

R. Wu, C. H. Chen, T. C. Huang, R. Beausoleil, and K. T. Cheng, “Spatial pattern analysis of process variations in silicon microring modulators,” in IEEE Optical Interconnects Conference (2016), pp. 116–117.

Beausoleil, R. G.

Bergman, K.

Bienstman, P.

Blaauw, D.

Bogaerts, W.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

Bojko, R.

Caverley, M.

N. Eid, H. Jayatilleka, M. Caverley, S. Shekhar, L. Chrostowski, and N. A. F. Jaeger, “Wide FSR silicon-on-insulator microring resonator with bent couplers,” IEEE 12th International Conference on Group IV Photonics (GFP, 2015), paper 96–97.

Chen, C. H.

Chen, X.

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Chen, Z.

Cheng, K. T.

Chew, W. C.

Chrostowski, L.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Optical Fiber Communication Conference (2014), paper. Th2A.37.
[Crossref]

L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
[Crossref]

Claes, T.

Cone, C.

Daniel, L.

Danziger, S.

Delvaux, C.

Dhaene, T.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Dumon, P.

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

Eid, N.

Faraon, A.

Fard, S. T.

Fattal, D.

Ferguson, J.

Fernandez, L.

Fiers, M.

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

Fiorentino, M.

Flückiger, J.

Flueckiger, J.

Galland, C.

Grist, S.

Guan, H.

Hautala, J.

Heyn, P. De

Hochberg, M.

L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
[Crossref]

Hsu, E. Y.

Huang, T. C.

Jaeger, N. A. F.

Jayatilleka, H.

Jhoja, J.

Keyvaninia, S.

Kim, C.

Klein, J.

Kumar Selvaraja, S.

LaRochelle, S.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Lavagno, L.

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

Lepage, G.

Li, A.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Li, S.

Li, Z.

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Lim, A. E.-J.

Liu, A.

Liu, Y.

Lo, G.-Q.

Locorotondo, S.

Lu, Z.

Ma, Y.

Martin, G.

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

Marzouk, Y.

Mashanovich, G. Z.

Melati, D.

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Melloni, A.

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Mickelson, A. R.

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Milenin, A.

Mohamed, M.

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Morichetti, F.

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Murdoch, G.

Nedeljkovic, M.

Ocheltree, S.

Ong, P.

Pathak, S.

Peng, Z.

Pond, J.

Reed, G. T.

Rosseel, E.

Santori, C.

Scheffer, L.

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

Schmid, J. H.

Sedra, A. S.

A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).

Selvaraja, S. K.

S. K. Selvaraja, “Wafer scale fabrication technology for silicon photonic integrated circuit,” Ph.D. thesis, Ghent University (2011).

Shang, L.

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

Shekhar, S.

Shi, W.

Simard, A. D.

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

Smith, K. C.

A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).

Song, J.

Spina, D.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Sterckx, G.

Su, Z.

Tabat, M.

Tai, W.

Thomson, D. J.

Thourhout, D. V.

Trotter, D. C.

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

Van Campenhout, J.

Van Thourhout, D.

Van Vaerenbergh, T.

Vos, K. De

Wagner, R. L.

Wang, X.

Wang, Y.

Watts, M. R.

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

Weng, T.-W.

Winroth, G.

Wu, R.

Wu, Y.

Xie, W.

Xing, Y.

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Xu, D. X.

Yang, S.

Yang, Y.

Yun, H.

Zhang, F.

Zhang, Y.

Zhang, Z.

Zolotov, V.

Zortman, W. A.

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

Adv. Opt. Photonics (1)

D. Melati, A. Melloni, and F. Morichetti, “Real photonic waveguides: guiding light through imperfections,” Adv. Opt. Photonics 6, 156–224 (2014).
[Crossref]

Appl. Opt. (1)

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref] [PubMed]

IEEE J. Sel. Top. Quantum Electron. (3)

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 1–8 (2014).
[Crossref]

IEEE Photonics Technol. Lett. (1)

N. Ayotte, A. D. Simard, and S. LaRochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photonics Technol. Lett. 27, 755–758 (2015).
[Crossref]

IEEE Trans. Antennas Prop. (1)

Laser Photonics Rev. (1)

Opt. Express (7)

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref] [PubMed]

Photonics Res. (1)

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photonics Res. 4, 93–100 (2016).
[Crossref]

Proc. SPIE (4)

Other (13)

S. K. Selvaraja, “Wafer scale fabrication technology for silicon photonic integrated circuit,” Ph.D. thesis, Ghent University (2011).

L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation, Circuit Design, and Process Technology (CRC, 2006).

A. S. Sedra and K. C. Smith, Microelectronic Circuits (Oxford University, 1998).

L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).
[Crossref]

https://www.klayout.de

https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK

https://www.lumerical.com

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Figures (23)

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Fig. 1 Proposed circuit simulation approach. First, the designer generates a layout and uses the netlist extraction tool to transfer the layout to a circuit simulator. Second, wafer-scale correlated variations are automatically simulated based on the characterized results from fabrication, and variations at each component position are assigned to the component. Then, the optical response of each component will automatically get updated according to obtained variations. Finally, circuit simulation is performed. Results include both common mode and differential mode variability.

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Fig. 2 (a) Cross-section schematic of an SOI strip waveguide; (b) effective index of strip waveguides for various waveguide widths; (c) effective index of strip waveguides for various waveguide heights.

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Fig. 3 (a) Schematic layout of the racetrack resonator test device; (b) transmission spectrum for such a device without fabrication variations. FSR is free-spectral-range.

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Fig. 4 Simulation results for racetrack resonators with a nominal waveguide height of 220 nm and various waveguide widths. (a) Transmission spectra; (b) group indices at resonances; (c) resonance wavelength versus waveguide width for a selected resonance mode; (d) group index versus waveguide width for a selected resonance mode.

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Fig. 5 Simulation results for racetrack resonators with a nominal waveguide width of 500 nm and various waveguide heights. (a) Transmission spectra; (b) group indices at resonances; (c) resonance wavelength versus waveguide height for a selected resonance mode; (d) group index versus waveguide height for a selected resonance mode.

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Fig. 6 Error test results in a Δw deviation range of ±20 nm and a Δh deviation range of ±10 nm, for the proposed variability characterization method. (a) Width extraction error; (b) height extraction error.

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Fig. 7 (a) Schematic layout for the fabricated racetrack resonator; (b) distribution of racetrack resonators on each wafer die; (c) wafer map for the fabricated multi-project-wafer.

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Fig. 8 Characterization results for the manufacturing variability a 200-mm-wafer. (a) Measured spectra for the 61 devices on die #20; (b) extracted n_g for the 61 devices on die #20; (c) extracted Δw versus position on die #20; (d) extracted Δh versus position on die #20; (e) extracted n_g versus λ_res for the 2074 devices on the wafer; (f) histogram for extracted Δw across the wafer; (g) histogram for extracted Δh across the wafer.

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Fig. 9 (a) Flow chart for the enhanced Monte Carlo methodology; (b) simulated virtual wafer for waveguide width deviations; (c) simulated virtual wafer for waveguide height deviations.

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Fig. 10 An example circuit consisting of two grating couplers connected by a waveguide. (a) Physical layout; (b) simulation schematic in the circuit simulator.

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Fig. 11 Illustration for the die selection and variation mapping of within-wafer analysis.

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Fig. 12 Illustration for the manufacturing variation simulations of wafer-to-wafer analysis.

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Fig. 13 (a) A 100 mm × 100 mm random distribution map z(x, y) generated with σ = 2; (b) a Gaussian filter map g(x, y) generated with l = 4 mm; (c) the correlated variation wafer map m(x, y).

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Fig. 14 (a) A 100 mm × 100 mm correlated variation wafer map m(x, y), which is simulated using a coarse simulation mesh; (b) and (c) are the variation maps for a 10 mm × 10 mm die located at the top right corner of the wafer before and after interpolation, respectively.

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Fig. 15 Diagram for Δw and Δh averaging in the waveguide compact model.

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Fig. 16 S-parameter component model. (a) Process corners for two process parameters: waveguide width variation, Δw, and height variation, Δh; (b) S-parameters for the nominal design, four process corners, and one interpolated geometry of a 2×2 splitter.

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Fig. 17 Layout decomposition examples of ring resonators. (a) All-pass ring resonator; (b) add-drop ring resonator.

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Fig. 18 A ring resonator based single-channel photonic filter circuit. (a) Physical layout; (b) circuit simulation schematic.

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Fig. 19 Simulation results for a ring resonator based single-channel filter. (a) ideal transmission spectrum; (b) transmission spectra on 3 representative dies with fabrication variations; (c) extracted group index versus resonance wavelength for the filter in 1600 simulations; (d) and (e) are histograms of resonance wavelengths and extinction ratios for the filter in 1600 simulations, respectively.

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Fig. 20 A photonic ring resonator based dual-channel filter circuit. (a) Physical layout; (b) circuit simulation schematic.

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Fig. 21 Simulation results for the ring resonator based dual-channel filter. (a) Output transmission spectra without fabrication variation; (b) and (c), respectively, are histograms for resonance wavelengths λ_res and channel spacings Δλ of the filter in 1600 simulations.

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Fig. 22 Histograms for the channel spacings for filter designs with d=30 μm, d=150 μm, and d=300 μm.

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Fig. 23 An example Mach-Zehnder interferometer circuit. (a) Circuit layout; (b) local pattern density for the Si layer of the layout, which is calculated using a 6 μm × 6 μm sampling window with a scanning step of 0.3 μm.

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Tables (7)

Table 1 Statistical results for the manufacturing variations of a 200-mm-wafer fabricated through a 248-nm DUV lithography process

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Table 2 Literature results for wafer-to-wafer fabrication variations

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Table 3 Literature results for within-wafer fabrication variations

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Table 4 Input parameters for the virtual wafer model

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Table 5 Monte Carlo analysis results for the ring resonator based single-channel filter

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Table 6 Monte Carlo analysis results for a dual-channel filter design with d=30 μm.

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Table 7 Monte Carlo analysis results for various dual-channel filters designs

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Equations (16)

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\frac{E_{t h r u}}{E_{i n}} = e^{i (π + \frac{2 π}{λ} n_{e f f} L)} \frac{a - t e^{- i \frac{2 π}{λ} n_{e f f} L}}{1 - t a e^{i \frac{2 π}{λ} n_{e f f} L}}

n_{g} = \frac{λ_{r e s}^{2}}{F S R \cdot L}

[\begin{matrix} Δ n_{g} \\ Δ λ_{r e s} \end{matrix}] = [\begin{matrix} \frac{\partial n_{g}}{\partial w} & \frac{\partial n_{g}}{\partial h} \\ \frac{\partial λ_{r e s}}{\partial w} & \frac{\partial λ_{r e s}}{\partial h} \end{matrix}] [\begin{matrix} Δ w \\ Δ h \end{matrix}]

[\begin{matrix} Δ w \\ Δ h \end{matrix}] = {[\begin{matrix} \frac{\partial n_{g}}{\partial w} & \frac{\partial n_{g}}{\partial h} \\ \frac{\partial λ_{r e s}}{\partial w} & \frac{\partial λ_{r e s}}{\partial h} \end{matrix}]}^{- 1} [\begin{matrix} Δ n_{g} \\ Δ λ_{r e s} \end{matrix}]

\frac{\partial λ_{r e s}}{\partial w} = 0.585911 (n m / n m)

\frac{\partial n_{g}}{\partial w} = - 0.001650 (/ n m)

\frac{\partial λ_{r e s}}{\partial h} = 1.36330 (n m / n m)

\frac{\partial n_{g}}{\partial h} = 0.001091 (/ n m)

E r r o r_{Δ w} = | Δ w_{g i v e n} - Δ w_{e x t r a c t e d} |; E r r o r_{Δ h} = | Δ h_{g i v e n} - Δ h_{e x t r a c t e d} |

g (x, y) = \frac{1}{\sqrt{π} \frac{l}{2}} e^{- (\frac{x^{2}}{l^{2} / 2} + \frac{y^{2}}{l^{2} / 2})}

m (x, y) = ℱ^{-} [ℱ [g (x, y)] \cdot ℱ [z (x, y)]]

m (x, y) = ℱ^{-} [ℱ [g (x, y)] \cdot ℱ [z (x, y)]] + c

n_{e f f} (λ) = n_{e f f} (λ_{0}) + (λ - λ_{0}) \cdot {\frac{d n_{e f f}}{d λ} |}_{λ = λ_{0}} + (λ - λ_{0}) {^{2} \cdot \frac{d^{2} n_{e f f}}{d λ^{2}} |}_{λ = λ_{0}}

n_{g} (λ_{0}) = n_{e f f} (λ_{0}) - λ_{0} \frac{d n_{e f f}}{d λ} |_{λ = λ_{0}}

D (λ_{0}) = - \frac{λ_{0}}{c} \frac{d^{2} n_{e f f}}{d λ^{2}} |_{λ = λ_{0}}

w_{a v g} = w_{0} + \frac{1}{N} \sum_{n = 1}^{N} Δ w_{n}, h_{a v g} = h_{0} + \frac{1}{N} \sum_{n = 1}^{N} h_{n}

	Δw	Δh
Mean, μ	7.709 nm	−1.72 nm
Standard deviation, σ	3.855 nm	1.316 nm

Process	Wafer-to-wafer variations
Process	$σ_{Δ w}^{*}$	$σ_{Δ h}^{*}$
imec 193-nm dry lithography [4]		1.26 nm

Process	Within-wafer variations
Process	σ_Δ_w	σ_Δ_h	l
imec 193-nm dry lithography [3, 4]	2.59 nm	2 nm
imec wafer-scale corrective etching [21]		0.83 nm
imec wafer-scale corrective etching [22]		3.64 nm
imec 193-nm immersion lithography [26]	2.53 nm
200 mm wafer, 193-nm dry lithography [24]	0.78 nm
300 mm wafer, 193-nm immersion lithography [24]	2.65 nm
BAE 248-nm lithography [14]			4.17 ± 0.42 mm
IME 248-nm lithography [13]			5 mm
imec 193-nm lithography [7]		2.4 nm
248-nm lithography [25]	2 nm	4.16 nm

Wafer size	Reticle size	Within-wafer			Wafer-to-wafer
Wafer size	Reticle size	σ_Δ_w	l_Δ_w	σ_Δ_h	l_Δ_h	$σ_{Δ w}^{*}$	$σ_{Δ h}^{*}$
200×200 mm²	5×5 mm²	3.855 nm	4.5 mm	1.316 nm	4.5 mm	0	0

	Resonance wavelength, λ_res (nm)	Extinction ratio, ER (dB)
Mean	1541.9	17.65
Standard deviation	2.799	0.555

	d = 30 μm	d = 150 μm	d = 300 μm
Mean for Δλ (nm)	8.991	8.990	8.992
Standard deviation for Δλ (nm)	0.050	0.146	0.279