Abstract

Large data centers interconnect bottlenecks are dominated by the switch I/O BW and the front panel BW as a result of pluggable modules. To overcome the front panel BW and the switch ASIC BW limitation one approach is to either move the optics onto the mid-plan or integrate the optics into the switch ASIC. Over the last 4 years, VCSEL based optical engines have been integrated into the packages of large-scale HPC routers, moderate size Ethernet switches, and even FPGA’s. Competing solutions based on Silicon Photonics (SiP) have also been proposed for integration into HPC and Ethernet switch packages but with better integration path through the use of TSV (Through Silicon Via) stack dies. Integrating either VCSEL or SiP based optical engines into complex ASIC package that operates at high temperatures, where the required reliability is not trivial, one should ask what is the technical or the economic advantage before embarking on such a complex integration. High density Ethernet switches addressing data centers currently in development are based on 25G NRZ signaling and QSFP28 optical module that can support up to 3.6 Tb of front panel bandwidth.

© 2015 Optical Society of America

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References

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  1. J. A. Kash1, A. F. Benner, F. E. Doany, D. M. Kuchta, B. G. Lee, P. K. Pepeljugoski, L. Schares, C. L. Schow, and M. Taubenblatt, “Optical interconnects in future servers”, OFC (2011), paper QWQ1.
  2. C. L. Schow, “Power efficient transceivers for high-bandwidth, short reach interconnects”, OFC (2012), paper OTh1E.4.
  3. A. Ghiasi, F. Tang, and S. Bhoja, IEEE 802.3, 100GNGOPTX study group. http://www.ieee802.org/3/100GNGOPTX/public/mar12/plenary/ghiasi_02_0312_NG100GOPTX.pdf .
  4. M. Watts, “Moore’s law, silicon photonics, and the remaining challenges”, HSD (2011).
  5. S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
    [Crossref]
  6. IEEE Std 802.3bj-2014 IEEE Standard for Ethernet Amendment 2: Physical Layer Specifications and Management Parameters for 100 Gb/s Operation Over Backplanes and Copper Cables.
  7. J. Bulzacchelli, T. Beukema, D. Storaska, P. Hsieh, S. Rylov, D. Furrer, D. Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, R. Kelkar, H. Ainspan, W. Kelly, G. Ritter, J. Garlett, R. Callan, T. Toifl, and D. Friedman, “A 28 Gb/s 4 tap FFE/15-tap DFE serial link Transceiver in 32 nm SOI CMOS technology”, Session 19.1, ISSCC (2012).
  8. A. Ghiasi, “Is there a need for on-chip photonic integration for large data warehouse switches”, IEEE Photonics Group IV, (2012).
  9. Optical Inter Networking Forum, http://www.oiforum.com/public/currentprojects.html .

2007 (1)

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Bhoja, S.

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Chang, F.

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Dudek, M.

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Ghiasi, A.

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Inano, S.

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Tsumura, E.

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

IEEE Communication Magazine, Vol (1)

S. Bhoja, A. Ghiasi, F. Chang, M. Dudek, S. Inano, and E. Tsumura, “Next-generation 10 Gbaud module based on emerging SFP+ with host-based EDC,” IEEE Communication Magazine, Vol 45(3), S32–S38 (2007).
[Crossref]

Other (8)

IEEE Std 802.3bj-2014 IEEE Standard for Ethernet Amendment 2: Physical Layer Specifications and Management Parameters for 100 Gb/s Operation Over Backplanes and Copper Cables.

J. Bulzacchelli, T. Beukema, D. Storaska, P. Hsieh, S. Rylov, D. Furrer, D. Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, R. Kelkar, H. Ainspan, W. Kelly, G. Ritter, J. Garlett, R. Callan, T. Toifl, and D. Friedman, “A 28 Gb/s 4 tap FFE/15-tap DFE serial link Transceiver in 32 nm SOI CMOS technology”, Session 19.1, ISSCC (2012).

A. Ghiasi, “Is there a need for on-chip photonic integration for large data warehouse switches”, IEEE Photonics Group IV, (2012).

Optical Inter Networking Forum, http://www.oiforum.com/public/currentprojects.html .

J. A. Kash1, A. F. Benner, F. E. Doany, D. M. Kuchta, B. G. Lee, P. K. Pepeljugoski, L. Schares, C. L. Schow, and M. Taubenblatt, “Optical interconnects in future servers”, OFC (2011), paper QWQ1.

C. L. Schow, “Power efficient transceivers for high-bandwidth, short reach interconnects”, OFC (2012), paper OTh1E.4.

A. Ghiasi, F. Tang, and S. Bhoja, IEEE 802.3, 100GNGOPTX study group. http://www.ieee802.org/3/100GNGOPTX/public/mar12/plenary/ghiasi_02_0312_NG100GOPTX.pdf .

M. Watts, “Moore’s law, silicon photonics, and the remaining challenges”, HSD (2011).

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Figures (5)

Fig. 1
Fig. 1 Ethernet bitrate, front panel bandwidth, and switch bandwidth.
Fig. 2
Fig. 2 A suitable 25/50 Gb/s BGA Ball Map.
Fig. 3
Fig. 3 Total I/O BW for given package size assuming 25G I/O.
Fig. 4
Fig. 4 Possible linecard implementations.
Fig. 5
Fig. 5 SerDes capability required for different line card implementation.

Tables (2)

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Table 1 10G, 40G, 100G, 200G, 400G module form factors

Tables Icon

Table 2 Power comparisons of 25G linecard implementations

Equations (1)

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TotalBW=2×R×[ ( m+n )×2R×8 ]×BW

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