Abstract

We report a defect state based guided-wave photoconductive detector at 1360–1630 nm telecommunication wavelength directly in standard microelectronics CMOS processes, with zero in-foundry process modification. The defect states in the polysilicon used to define a transistor gate assists light absorption. The body crystalline silicon helps form an inverse ridge waveguide to confine optical mode. The measured responsivity and dark current at 25 V forward bias are 0.34 A/W and 1.4 μA, respectively. The 3 dB bandwidth of the device is 1 GHz.

© 2015 Optical Society of America

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2015 (1)

L. Alloatti, S. A. Srinivasan, J. S. Orcutt, and R. J. Ram, “Waveguide-coupled detector in zero-change complementary metaloxidesemiconductor,” Appl. Phys. Lett. 107, 041104 (2015).
[Crossref]

2014 (4)

A. Yaacobi, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “Integrated phased array for wide-angle beam steering,” Opt. Lett. 39, 4575–4578 (2014).
[Crossref] [PubMed]

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

K. K. Mehta, J. S. Orcutt, J. M. Shainline, O. Tehar-Zahav, Z. Sternberg, R. Meade, M. A. Popovi, and R. J. Ram, “Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process,” Opt. Lett. 39, 1061–1064 (2014).
[Crossref] [PubMed]

K. K. Mehta, J. S. Orcutt, O. Tehar-Zahav, Z. Sternberg, R. Bafrali, R. Meade, and R. J. Ram, “High-Q CMOS-integrated photonic crystal microcavity devices,” Sci. Rep. 4, 4077 (2014).
[Crossref] [PubMed]

2013 (4)

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
[Crossref] [PubMed]

J. Sun, E. Timurdogan, A. Yaacobi, E. S. Hosseini, and M. R. Watts, “Large-scale nanophotonic phased array,” Nature 493, 195–199 (2013).
[Crossref] [PubMed]

K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
[Crossref]

J. J. Ackert, A. S. Karar, D. J. Paez, P. E. Jessop, J. C. Cartledge, and A. P. Knights, “10 Gbps silicon waveguide-integrated infrared avalanche photodiode,” Opt. Express 21, 19530–19537 (2013).
[Crossref] [PubMed]

2012 (2)

2011 (2)

2009 (3)

K. Wada, P. Sungbong, and Y. Ishikawa, “Si photonics and fiber to the home,” Proc. IEEE 97, 1329–1336 (2009).
[Crossref]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
[Crossref] [PubMed]

2007 (1)

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
[Crossref]

2005 (1)

C. Niclass, A. Rochas, P. A. Besse, and E. Charbon, “Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes,” IEEE J. Solid-State Circuits 40, 1847–1854 (2005).
[Crossref]

2002 (1)

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Abdalla, S.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Ackert, J. J.

Adachi, K.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Ahn, J. H.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Alloatti, L.

L. Alloatti, S. A. Srinivasan, J. S. Orcutt, and R. J. Ram, “Waveguide-coupled detector in zero-change complementary metaloxidesemiconductor,” Appl. Phys. Lett. 107, 041104 (2015).
[Crossref]

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Asanovic, K.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

Assefa, S.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Atabaki, A.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Azuma, A.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Bae, G. J.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Bafrali, R.

K. K. Mehta, J. S. Orcutt, O. Tehar-Zahav, Z. Sternberg, R. Bafrali, R. Meade, and R. J. Ram, “High-Q CMOS-integrated photonic crystal microcavity devices,” Sci. Rep. 4, 4077 (2014).
[Crossref] [PubMed]

Barwicz, T.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Batten, C.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

Besse, P. A.

C. Niclass, A. Rochas, P. A. Besse, and E. Charbon, “Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes,” IEEE J. Solid-State Circuits 40, 1847–1854 (2005).
[Crossref]

Bonifield, T.

Butrie, T.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Carey, J. E.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Cartledge, J. C.

Charbon, E.

C. Niclass, A. Rochas, P. A. Besse, and E. Charbon, “Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes,” IEEE J. Solid-State Circuits 40, 1847–1854 (2005).
[Crossref]

Chen, J. P.

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

Chen, Y. H.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Coolbaugh, D.

Damle, A.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

De Dobbelaere, P. M.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Debnath, K.

K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
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Deneault, S.

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
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M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Dhar, N. K.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Ellis-Monaghan, J.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Foltz, D.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Fuchikami, T.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Fujiwara, M.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Fukui, H.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Gan, F.

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
[Crossref]

Gardes, F. Y.

K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
[Crossref]

Geis, M. W.

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
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M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
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Georgas, M.

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
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J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
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M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

Gill, D. M.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Gloeckner, S.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Green, W.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Grein, M. E.

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
[Crossref] [PubMed]

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
[Crossref]

Haddad, H.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Haensch, W.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Haldar, P.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Hofrichter, J.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Hokazono, A.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Hollingsworth, R.

Holzwarth, C. W.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
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C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
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Horst, F.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Hosseini, E. S.

J. Sun, E. Timurdogan, A. Yaacobi, E. S. Hosseini, and M. R. Watts, “Large-scale nanophotonic phased array,” Nature 493, 195–199 (2013).
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Hovey, S.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Hoyt, J. L.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
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Huapu, P.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Iinuma, T.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Inaba, S.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Ishikawa, Y.

K. Wada, P. Sungbong, and Y. Ishikawa, “Si photonics and fiber to the home,” Proc. IEEE 97, 1329–1336 (2009).
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Ishiuchi, H.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Ishizuka, S.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Itani, T.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Jackson, S.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Jeon, C. H.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Jessop, P. E.

Jiang, J.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Joshi, A.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
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Jung, K. S.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Jung, M. K.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Kaertner, F. X.

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
[Crossref]

Kamlapurkar, S.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Kang, H. S.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Karar, A. S.

Kartner, F. X.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
[Crossref] [PubMed]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
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Kato, M.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Katsumata, Y.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Khater, M.

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Khayam, O.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Khilo, A.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
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Kiewra, E.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Kim, K. S.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Kim, Y. W.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Kish, F.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

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K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
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Ko, Y. G.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Kramer, S.

Krause, D.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Krauss, T. F.

K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
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Kudo, T.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Kumar, R.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

Kuntz, M.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Lal, V.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Lambert, D.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Leake, G.

Lee, D. H.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Lee, J.-U.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Lee, K. T.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Lee, N. I.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Lee, S. G.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Lee, Y. H. D.

Lennon, D. M.

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
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M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
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Leu, J.

Leu, J. C.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Li, H. Q.

Li, X.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Li, X. W.

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

Liang, Y.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Lin, S.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Lipson, M.

Liu, S. H.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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Lyszczarz, T. M.

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
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M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
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Mack, M.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Maekawa, T.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Malendevich, R.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Masini, G.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Matsuda, S.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Matsushima, O.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

McKee, J.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

McNicol, J.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Meade, R.

Mehta, K.

Mehta, K. K.

Mekis, A.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Min, Y.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Missey, M.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Miyazaki, K.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Moresco, M.

Mori, S.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
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Moriwake, M.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Moss, B.

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
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J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
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C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Moss, B. R.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Murakoshi, A.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Nagarajan, R.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Nammari, K.

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
[Crossref] [PubMed]

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Niclass, C.

C. Niclass, A. Rochas, P. A. Besse, and E. Charbon, “Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes,” IEEE J. Solid-State Circuits 40, 1847–1854 (2005).
[Crossref]

Niki, S.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

O’Faolain, L.

K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
[Crossref]

Offrein, B.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Oguma, H.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Oh, B. J.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Oh, C. B.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Ohuchi, K.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Okano, K.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Orcutt, J.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

Orcutt, J. S.

L. Alloatti, S. A. Srinivasan, J. S. Orcutt, and R. J. Ram, “Waveguide-coupled detector in zero-change complementary metaloxidesemiconductor,” Appl. Phys. Lett. 107, 041104 (2015).
[Crossref]

K. K. Mehta, J. S. Orcutt, O. Tehar-Zahav, Z. Sternberg, R. Bafrali, R. Meade, and R. J. Ram, “High-Q CMOS-integrated photonic crystal microcavity devices,” Sci. Rep. 4, 4077 (2014).
[Crossref] [PubMed]

K. K. Mehta, J. S. Orcutt, J. M. Shainline, O. Tehar-Zahav, Z. Sternberg, R. Meade, M. A. Popovi, and R. J. Ram, “Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process,” Opt. Lett. 39, 1061–1064 (2014).
[Crossref] [PubMed]

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
[Crossref] [PubMed]

J. S. Orcutt, S. D. Tang, S. Kramer, K. Mehta, H. Q. Li, V. Stojanovic, and R. J. Ram, “Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process,” Opt. Express 20, 7243–7254 (2012).
[Crossref] [PubMed]

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
[Crossref] [PubMed]

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
[Crossref] [PubMed]

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

Oyamatsu, H.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Paez, D. J.

Palsule, C.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Park, M. H.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Park, T. S.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Pavanello, F.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Peterson, M.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Pethuraja, G.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Pinguet, T.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Popovi, M. A.

Popovic, M.

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
[Crossref] [PubMed]

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Popovic, M. A.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
[Crossref] [PubMed]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Pralle, M. U.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Preston, K.

Proesel, J.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Puri, Y. R.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Rahn, J.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Ram, R.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Ram, R. J.

L. Alloatti, S. A. Srinivasan, J. S. Orcutt, and R. J. Ram, “Waveguide-coupled detector in zero-change complementary metaloxidesemiconductor,” Appl. Phys. Lett. 107, 041104 (2015).
[Crossref]

K. K. Mehta, J. S. Orcutt, O. Tehar-Zahav, Z. Sternberg, R. Bafrali, R. Meade, and R. J. Ram, “High-Q CMOS-integrated photonic crystal microcavity devices,” Sci. Rep. 4, 4077 (2014).
[Crossref] [PubMed]

K. K. Mehta, J. S. Orcutt, J. M. Shainline, O. Tehar-Zahav, Z. Sternberg, R. Meade, M. A. Popovi, and R. J. Ram, “Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process,” Opt. Lett. 39, 1061–1064 (2014).
[Crossref] [PubMed]

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
[Crossref] [PubMed]

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
[Crossref] [PubMed]

J. S. Orcutt, S. D. Tang, S. Kramer, K. Mehta, H. Q. Li, V. Stojanovic, and R. J. Ram, “Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process,” Opt. Express 20, 7243–7254 (2012).
[Crossref] [PubMed]

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
[Crossref] [PubMed]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Reed, G. T.

K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
[Crossref]

Reffle, M.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Reinholm, C.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Rice, P.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Richwine, R. A.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Rochas, A.

C. Niclass, A. Rochas, P. A. Besse, and E. Charbon, “Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes,” IEEE J. Solid-State Circuits 40, 1847–1854 (2005).
[Crossref]

Rosenberg, J.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Rylyakov, A.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Sahebi, F.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Sahni, S.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Sakurai, K.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Schow, C.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Schulein, R. T.

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
[Crossref]

Sekiguchi, H.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Shainline, J.

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
[Crossref] [PubMed]

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Shainline, J. M.

Shank, S.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Sharp, M.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Shibata, H.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Shimizu, T.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Sickler, J.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Smith, H. I.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
[Crossref] [PubMed]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

Song, W. S.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Sood, A. K.

A. K. Sood, R. A. Richwine, G. Pethuraja, Y. R. Puri, J.-U. Lee, P. Haldar, and N. K. Dhar, “Design and development of wafer-level short wave infrared micro-camera,” in SPIE Defense, Security and Sensing (SPIE, 2013), pp. 870439–870410.

Spector, S. J.

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
[Crossref] [PubMed]

M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
[Crossref]

Srinivasan, A.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Srinivasan, S. A.

L. Alloatti, S. A. Srinivasan, J. S. Orcutt, and R. J. Ram, “Waveguide-coupled detector in zero-change complementary metaloxidesemiconductor,” Appl. Phys. Lett. 107, 041104 (2015).
[Crossref]

Sternberg, Z.

Stojanovi, V.

Stojanovic, V.

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
[Crossref] [PubMed]

J. S. Orcutt, S. D. Tang, S. Kramer, K. Mehta, H. Q. Li, V. Stojanovic, and R. J. Ram, “Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process,” Opt. Express 20, 7243–7254 (2012).
[Crossref] [PubMed]

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Q. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kartner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19, 2335–2346 (2011).
[Crossref] [PubMed]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
[Crossref]

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Suguro, K.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Suh, K. P.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Sun, C.

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
[Crossref] [PubMed]

J. S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Q. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram, and V. Stojanovic, “Open foundry platform for high-performance electronic-photonic integration,” Opt. Express 20, 12222–12232 (2012).
[Crossref] [PubMed]

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

Sun, H.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Sun, J.

Sun, P.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Sungbong, P.

K. Wada, P. Sungbong, and Y. Ishikawa, “Si photonics and fiber to the home,” Proc. IEEE 97, 1329–1336 (2009).
[Crossref]

Suto, H.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Takaoka, M.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Takasu, H.

O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Takayanagi, M.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Tan, D.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Tang, J.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Tang, S. D.

Taniguchi, S.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Tehar-Zahav, O.

Timurdogan, E.

J. Sun, E. Timurdogan, A. Yaacobi, E. S. Hosseini, and M. R. Watts, “Large-scale nanophotonic phased array,” Nature 493, 195–199 (2013).
[Crossref] [PubMed]

Topuria, T.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Toyoshima, Y.

S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide,” IEEE Trans. Electron Devices 49, 2263–2270 (2002).
[Crossref]

Tsai, H. S.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Urosevic, S.

Verslegers, L.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Vineis, C.

M. U. Pralle, J. E. Carey, H. Haddad, C. Vineis, J. Sickler, X. Li, J. Jiang, F. Sahebi, C. Palsule, and J. McKee, “IR CMOS: infrared enhanced silicon imaging,” in SPIE Defense, Security and Sensing (2013), paper 870407.

Vlasov, Y.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Wada, K.

K. Wada, P. Sungbong, and Y. Ishikawa, “Si photonics and fiber to the home,” Proc. IEEE 97, 1329–1336 (2009).
[Crossref]

Wade, M.

C. Sun, M. Wade, M. Georgas, S. Lin, L. Alloatti, B. Moss, R. Kumar, A. Atabaki, F. Pavanello, R. Ram, M. Popovic, and V. Stojanovic, “A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning,” in Symposium on VLSI Circuits, (2015), pp. C122–C123.

M. Georgas, B. R. Moss, C. Sun, J. Shainline, J. S. Orcutt, M. Wade, Y. H. Chen, K. Nammari, J. C. Leu, A. Srinivasan, R. J. Ram, M. A. Popovic, and V. Stojanovic, “A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process,” in Symposium on VLSI Circuits (2014), pp. 1–2.

Wade, M. T.

J. M. Shainline, J. S. Orcutt, M. T. Wade, K. Nammari, B. Moss, M. Georgas, C. Sun, R. J. Ram, V. Stojanovi, and M. A. Popovi, “Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS,” Opt. Lett. 38, 2657–2659 (2013).
[Crossref] [PubMed]

M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

Watts, M. R.

A. Yaacobi, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “Integrated phased array for wide-angle beam steering,” Opt. Lett. 39, 4575–4578 (2014).
[Crossref] [PubMed]

J. Sun, E. Timurdogan, A. Yaacobi, E. S. Hosseini, and M. R. Watts, “Large-scale nanophotonic phased array,” Nature 493, 195–199 (2013).
[Crossref] [PubMed]

Weaver, M.

Wee, Y. G.

Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
[Crossref]

Welch, B. P.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Welch, D.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Wu, K. T.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Wu, Q. Q.

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

Xiaoxiong, G.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

Yaacobi, A.

A. Yaacobi, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “Integrated phased array for wide-angle beam steering,” Opt. Lett. 39, 4575–4578 (2014).
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J. Sun, E. Timurdogan, A. Yaacobi, E. S. Hosseini, and M. R. Watts, “Large-scale nanophotonic phased array,” Nature 493, 195–199 (2013).
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O. Matsushima, K. Miyazaki, M. Takaoka, T. Maekawa, H. Sekiguchi, T. Fuchikami, M. Moriwake, H. Takasu, S. Ishizuka, K. Sakurai, A. Yamada, and S. Niki, “A high-sensitivity broadband image sensor using CuInGaSe2 thin films,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2008), pp. 1–4.

Yokoyama, K.

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Yoon, J. U.

M. W. Geis, S. J. Spector, M. E. Grein, J. U. Yoon, D. M. Lennon, and T. M. Lyszczarz, “Silicon waveguide infrared photodiodes with 35 GHz bandwidth and phototransistors with 50 AW(−1) response,” Opt. Express 17, 5193–5204 (2009).
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M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
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Y. W. Kim, C. B. Oh, Y. G. Ko, K. T. Lee, J. H. Ahn, T. S. Park, H. S. Kang, D. H. Lee, M. K. Jung, H. J. Yu, K. S. Jung, S. H. Liu, B. J. Oh, K. S. Kim, N. I. Lee, M. H. Park, G. J. Bae, S. G. Lee, W. S. Song, Y. G. Wee, C. H. Jeon, and K. P. Suh, “50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2002), pp. 69–72.
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A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

Zgraggen, E.

Zhang, J. M.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

Zhang, M. A.

Zhou, L. J.

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

Zhou, Y. Y.

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

Zhu, H. K.

H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

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L. Alloatti, S. A. Srinivasan, J. S. Orcutt, and R. J. Ram, “Waveguide-coupled detector in zero-change complementary metaloxidesemiconductor,” Appl. Phys. Lett. 107, 041104 (2015).
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K. Debnath, F. Y. Gardes, A. P. Knights, G. T. Reed, T. F. Krauss, and L. O’Faolain, “Dielectric waveguide vertically coupled to all-silicon photodiodes operating at telecommunication wavelengths,” Appl. Phys. Lett. 102, 171106 (2013).
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H. K. Zhu, L. J. Zhou, Y. Y. Zhou, Q. Q. Wu, X. W. Li, and J. P. Chen, “All-silicon waveguide avalanche photodetectors with ultrahigh gain-bandwidth product and low breakdown voltage,” IEEE J. Sel. Top. Quantum Electron. 20, 3803006 (2014).

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C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic Cmos silicon photonics,” IEEE Micro. 29, 8–21 (2009).
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M. W. Geis, S. J. Spector, M. E. Grein, R. T. Schulein, J. U. Yoon, D. M. Lennon, S. Deneault, F. Gan, F. X. Kaertner, and T. M. Lyszczarz, “CMOS-compatible all-Si high-speed waveguide photodiodes with high responsivity in near-infrared communication band,” IEEE Photonics Technol. Lett. 19, 152–154 (2007).
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M. T. Wade, J. M. Shainline, J. S. Orcutt, C. Sun, R. Kumar, B. Moss, M. Georgas, R. J. Ram, V. Stojanovic, and M. A. Popovic, “Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process,” in Optical Fiber Communications Conference and Exhibition (OFC, 2014), pp. 1–3.

M. Kato, R. Malendevich, D. Lambert, M. Kuntz, A. Damle, V. Lal, A. Dentai, O. Khayam, R. Nagarajan, J. Tang, J. M. Zhang, H. S. Tsai, T. Butrie, M. Missey, J. Rahn, D. Krause, J. McNicol, K. T. Wu, H. Sun, M. Reffle, F. Kish, and D. Welch, “10 Channel, 28 Gbaud PM-QPSK, monolithic InP terabit superchannel receiver PIC,” IEEE Photonics Conf., 340–341 (2011).

A. Mekis, S. Abdalla, D. Foltz, S. Gloeckner, S. Hovey, S. Jackson, Y. Liang, M. Mack, G. Masini, M. Peterson, T. Pinguet, S. Sahni, M. Sharp, P. Sun, D. Tan, L. Verslegers, B. P. Welch, K. Yokoyama, S. Yu, and P. M. De Dobbelaere, “A CMOS photonics platform for high-speed optical interconnects,” in IEEE Photonics Conference (IPC) (IEEE, 2012), pp. 356–357.

S. Assefa, S. Shank, W. Green, M. Khater, E. Kiewra, C. Reinholm, S. Kamlapurkar, A. Rylyakov, C. Schow, F. Horst, P. Huapu, T. Topuria, P. Rice, D. M. Gill, J. Rosenberg, T. Barwicz, Y. Min, J. Proesel, J. Hofrichter, B. Offrein, G. Xiaoxiong, W. Haensch, J. Ellis-Monaghan, and Y. Vlasov, “A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications,” in IEEE International Electron Devices Meeting (IEDM) (IEEE, 2012), paper 33.38.31.

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Figures (8)

Fig. 1
Fig. 1 (a) Polysilicon density of states (DOS) showing defect states in polysilicon assisting sub-bandgap photon absorption and electron-hole pairs generation [22]. (b) Transmission electron micrograph of gate polysilicon showing the grain structure and the surface roughness [21].
Fig. 2
Fig. 2 (a) Cross-section of a typical n-type MOSFET in SOI CMOS. (b) Cross-section of an inverse ridge waveguide formed by polysilicon cap and crystalline silicon ridge. (c) Mode profile of the inverse ridge waveguide. (d) Bird’s eye view of the micro-ring photodetector. Tapers are used to reduce coupling loss between crystalline silicon waveguide and inverse ridge waveguide. Vertical grating couplers are used to couple light with off-chip fibers.(e) Cross section of the coupling region. The gap size between two crystalline silicon ridge determine the coupling strength. (f) Mode profile of the coupling region.
Fig. 3
Fig. 3 (a) Crystalline silicon ridge width of 600 nm keep confinement factors in S/D region small Additionally, it also reduce confinement factor above polysilicon. (b) Central polysilicon width of 1.6 μm reduces the confinement in S/D region to below 0.1%.
Fig. 4
Fig. 4 (a) Photo of the front side of the photodetector. The device is under the fill shapes of the top metal layers that are only blocked from the vertical grating couplers to enable coupling into the chip. The GSG contact pads are connected to the two device terminals through vias and metal interconnect layers. (b) Photo of back side of the device after the silicon substrate is completely removed in a Xenon Difluoride etch chamber. (c) Photo of the back side of the die. Electronic circuits and photonic devices are integrated monolithically.
Fig. 5
Fig. 5 (a) Resonance is achieved from 1520 nm to 1580 nm. The FSR is around 9 nm. (b) Highest extinction is obtained at gap size of 160 nm. Gap sizes between 130 nm and 190 nm production extinction more than 10 dB.
Fig. 6
Fig. 6 (a) I–V curves of the resonant photodetector without and with 40 μW light launched into the waveguide. The inset shows a close-up of the I–V curve near the 0 V bias showing an open-circuit voltage. (b) Responsivity at 1550 nm versus bias voltage with 40 μW optical power into the device.
Fig. 7
Fig. 7 (a) Responsivity of the resonant photodetector as a function of the optical power entering the resonator at 1570 nm under 5 V reverse (red curve) and forward (blue curve) bias. (b) Responsivity of the photodetector from 1360 nm to 1630 nm for 20μW optical power entering the resonator normalized to responsivity at 1550 nm with 5 V forward bias.
Fig. 8
Fig. 8 The 3 dB bandwidth under both forward and reverse bias is around 1 GHz

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