Abstract

With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

© 2015 Optical Society of America

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References

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  1. P. Maniotis, D. Fitsios, G. T. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
    [Crossref]
  2. B. Jacob, S. W. Ng, and D. T. Wang, “DRAM memory system organization,” in Memory System: Cache, DRAM, Disk, C. Glaser, P. Gottehrer, N. McFadden, and K. Honjo, eds. (Morgan Kaufmann, 2008), pp. 409–424.
  3. S. Beamer, C. Sun, Y. J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, “Re-architecting DRAM memory systems with monolithically integrated silicon photonics,” in Proceedings of International Symposium on Computer Architecture, (ASSOC COMPUTING MACHINERY, 2010), pp. 129–140.
    [Crossref]
  4. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
    [Crossref]
  5. H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
    [Crossref]
  6. K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Proceedings of Conference on Optical Fiber Communication and Exposition and the National Fiber Optic Engineers Conference (OPTICAL SOC AMERICA, 2011), pp. 1–3.
    [Crossref]
  7. D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
    [Crossref]
  8. D. Brunina, L. Dawei, and K. Bergman, “An energy-efficient optically connected memory module for hybrid packet- and circuit-switched optical networks,” IEEE J. Sel. Top. Quantum Electron. 19(2), 3700407 (2013).
    [Crossref]
  9. X. Yuan, “Future memory and interconnect technologies,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (IEEE, 2013), pp. 964–969.
  10. C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
    [Crossref]
  11. Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
    [Crossref]
  12. A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
    [Crossref]
  13. X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
    [Crossref] [PubMed]
  14. P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory system simulator,” IEEE Comput. Archit. Lett. 10(1), 16–19 (2011).
    [Crossref]
  15. J. Hestness and S. W. Keckler, “Netrace: dependency-tracking traces for efficient network-on-chip experimentation,” Technical Report TR-10–11, The University of Texas at Austin, Department of Computer Science, May 2011.
  16. C. Bienia and K. Li, “Fidelity and scaling of the PARSEC benchmark inputs,” in Proceedings of IEEE International Symposium on Workload Characterization (IEEE, 2010), pp. 1–10.
    [Crossref]
  17. R. Giordano and A. Aloisio, “Fixed-latency, multi-gigabit serial links with xilinx FPGAs,” IEEE Trans. Nucl. Sci. 58(1), 194–201 (2011).
    [Crossref]
  18. Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).
  19. X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
    [Crossref]
  20. A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
    [Crossref]
  21. A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
    [Crossref]
  22. R. Hendry, D. Nikolova, S. Rumley, and K. Bergman, “Modeling and evaluation of chip-to-chip scale silicon photonic networks,” in Proceedings of 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects (IEEE, 2014), pp. 1–8.
    [Crossref]
  23. G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.
  24. E. E. Hussein, S. Safwat, M. Ghoneima, and Y. Ismail, “A new signaling technique for a low power on-chip SerDes transceivers,” in Proceedings of International Conference on Energy Aware Computing (IEEE, 2010), pp. 1–2.
    [Crossref]
  25. K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.
  26. S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE J. Sel. Top. Quantum Electron. 19(2), 8200109 (2013).
    [Crossref]
  27. P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. S. Williams, and K. Yelick, “Exascale computing study: technology challenges in achieving exascale systems,” Dep. CSE, Univ. Notre Dane, IN, USA, Rep. TR-2008–13, Sept. 2008.

2014 (2)

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

2013 (3)

S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE J. Sel. Top. Quantum Electron. 19(2), 8200109 (2013).
[Crossref]

P. Maniotis, D. Fitsios, G. T. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
[Crossref]

D. Brunina, L. Dawei, and K. Bergman, “An energy-efficient optically connected memory module for hybrid packet- and circuit-switched optical networks,” IEEE J. Sel. Top. Quantum Electron. 19(2), 3700407 (2013).
[Crossref]

2011 (3)

P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory system simulator,” IEEE Comput. Archit. Lett. 10(1), 16–19 (2011).
[Crossref]

R. Giordano and A. Aloisio, “Fixed-latency, multi-gigabit serial links with xilinx FPGAs,” IEEE Trans. Nucl. Sci. 58(1), 194–201 (2011).
[Crossref]

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

2010 (1)

Ahn, J. H.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Aloisio, A.

R. Giordano and A. Aloisio, “Fixed-latency, multi-gigabit serial links with xilinx FPGAs,” IEEE Trans. Nucl. Sci. 58(1), 194–201 (2011).
[Crossref]

Alon, E.

Amberg, P.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Asghari, M.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Audzevich, Y.

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

Beausoleil, R. G.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Bergman, K.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

D. Brunina, L. Dawei, and K. Bergman, “An energy-efficient optically connected memory module for hybrid packet- and circuit-switched optical networks,” IEEE J. Sel. Top. Quantum Electron. 19(2), 3700407 (2013).
[Crossref]

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

R. Hendry, D. Nikolova, S. Rumley, and K. Bergman, “Modeling and evaluation of chip-to-chip scale silicon photonic networks,” in Proceedings of 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects (IEEE, 2014), pp. 1–8.
[Crossref]

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

Biberman, A.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

Bienia, C.

C. Bienia and K. Li, “Fidelity and scaling of the PARSEC benchmark inputs,” in Proceedings of IEEE International Symposium on Workload Characterization (IEEE, 2010), pp. 1–10.
[Crossref]

Binkert, N.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Brunina, D.

D. Brunina, L. Dawei, and K. Bergman, “An energy-efficient optically connected memory module for hybrid packet- and circuit-switched optical networks,” IEEE J. Sel. Top. Quantum Electron. 19(2), 3700407 (2013).
[Crossref]

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

Byun, H.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Chan, J.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

Chen, C.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Cho, K.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Choi, J.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Choi, S.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Chung, C.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Contu, P.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Coolbaugh, D.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Cooper-Balis, E.

P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory system simulator,” IEEE Comput. Archit. Lett. 10(1), 16–19 (2011).
[Crossref]

Coskun, A. K.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Cunningham, J.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Cunningham, J. E.

Davis, A.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Dawei, L.

D. Brunina, L. Dawei, and K. Bergman, “An energy-efficient optically connected memory module for hybrid packet- and circuit-switched optical networks,” IEEE J. Sel. Top. Quantum Electron. 19(2), 3700407 (2013).
[Crossref]

Dong, P.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Dutt, R.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

Feng, D.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Fiorentino, M.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Fitsios, D.

Ghoneima, M.

E. E. Hussein, S. Safwat, M. Ghoneima, and Y. Ismail, “A new signaling technique for a low power on-chip SerDes transceivers,” in Proceedings of International Conference on Energy Aware Computing (IEEE, 2010), pp. 1–2.
[Crossref]

Giordano, R.

R. Giordano and A. Aloisio, “Fixed-latency, multi-gigabit serial links with xilinx FPGAs,” IEEE Trans. Nucl. Sci. 58(1), 194–201 (2011).
[Crossref]

Glick, M.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

Ha, K.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Han, S.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Hargrove, P.

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Hemmert, K. S.

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Hendry, G.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Hendry, R.

R. Hendry, D. Nikolova, S. Rumley, and K. Bergman, “Modeling and evaluation of chip-to-chip scale silicon photonic networks,” in Proceedings of 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects (IEEE, 2014), pp. 1–8.
[Crossref]

Ho, R.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Hong, S.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Hussein, E. E.

E. E. Hussein, S. Safwat, M. Ghoneima, and Y. Ismail, “A new signaling technique for a low power on-chip SerDes transceivers,” in Proceedings of International Conference on Energy Aware Computing (IEEE, 2010), pp. 1–2.
[Crossref]

Hyun, S.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Ismail, Y.

E. E. Hussein, S. Safwat, M. Ghoneima, and Y. Ismail, “A new signaling technique for a low power on-chip SerDes transceivers,” in Proceedings of International Conference on Energy Aware Computing (IEEE, 2010), pp. 1–2.
[Crossref]

Jacob, B.

P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory system simulator,” IEEE Comput. Archit. Lett. 10(1), 16–19 (2011).
[Crossref]

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Jeong, T.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Ji, H.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Joe, I.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Joshi, A.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Jouppi, N. P.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Kanellos, G. T.

Kim, J.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Kim, K.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Kim, S.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Klamkin, J.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Krishnamoorthy, A. V.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Kwon, H.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Leake, G.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Lee, B.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Lee, H.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Lee, K.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Levy, J. S.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

Lexau, J.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Li, G.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Li, K.

C. Bienia and K. Li, “Fidelity and scaling of the PARSEC benchmark inputs,” in Proceedings of IEEE International Symposium on Workload Characterization (IEEE, 2010), pp. 1–10.
[Crossref]

Liao, S.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Lipson, M.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE J. Sel. Top. Quantum Electron. 19(2), 8200109 (2013).
[Crossref]

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

Liu, F.

Long, C.

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

Luo, L.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

Luo, Y.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Maniotis, P.

Manipatruni, S.

S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE J. Sel. Top. Quantum Electron. 19(2), 8200109 (2013).
[Crossref]

McLaren, M.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Mekis, A.

Monchiero, M.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Moore, A. W.

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

Moore, S. W.

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

Moresco, M.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Mujumdar, A.

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

Na, K.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Nam, J.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Nikolova, D.

R. Hendry, D. Nikolova, S. Rumley, and K. Bergman, “Modeling and evaluation of chip-to-chip scale silicon photonic networks,” in Proceedings of 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects (IEEE, 2014), pp. 1–8.
[Crossref]

Padmaraju, K.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

Park, Y.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Patil, D.

Pinckney, N.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Pinguet, T.

Pleros, N.

Preston, K.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

Pyo, J.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Raj, K.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Resnick, D.

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Rodrigues, A.

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Rosenfeld, P.

P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory system simulator,” IEEE Comput. Archit. Lett. 10(1), 16–19 (2011).
[Crossref]

Rumley, S.

R. Hendry, D. Nikolova, S. Rumley, and K. Bergman, “Modeling and evaluation of chip-to-chip scale silicon photonic networks,” in Proceedings of 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects (IEEE, 2014), pp. 1–8.
[Crossref]

Safwat, S.

E. E. Hussein, S. Safwat, M. Ghoneima, and Y. Ismail, “A new signaling technique for a low power on-chip SerDes transceivers,” in Proceedings of International Conference on Energy Aware Computing (IEEE, 2010), pp. 1–2.
[Crossref]

Schreiber, R.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Shafiiha, R.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Shalf, J.

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

Sherwood-Droz, N.

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

Shi, J.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Shin, D.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Shin, Y.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Su, Z.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Suh, S.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Sun, J.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Thacker, H.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Timurdogan, E.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Vantrease, D.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

Watts, M. R.

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

Watts, P. M.

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

West, A.

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

Yang, S.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

Yao, J.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Yoon, H.

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

Young, I. A.

S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE J. Sel. Top. Quantum Electron. 19(2), 8200109 (2013).
[Crossref]

Zhang, T.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Zheng, D.

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Zheng, X.

X. Zheng, F. Liu, D. Patil, H. Thacker, Y. Luo, T. Pinguet, A. Mekis, J. Yao, G. Li, J. Shi, K. Raj, J. Lexau, E. Alon, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems,” Opt. Express 18(1), 204–211 (2010).
[Crossref] [PubMed]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

Zhu, X.

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

ACM J EMERG TECHNOL (1)

A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, J. S. Levy, M. Lipson, and K. Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high performance chip,” ACM J EMERG TECHNOL 7(2), 1–25 (2011).
[Crossref]

IEEE Comput. Archit. Lett. (1)

P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory system simulator,” IEEE Comput. Archit. Lett. 10(1), 16–19 (2011).
[Crossref]

IEEE J. Sel. Top. Quantum Electron. (2)

D. Brunina, L. Dawei, and K. Bergman, “An energy-efficient optically connected memory module for hybrid packet- and circuit-switched optical networks,” IEEE J. Sel. Top. Quantum Electron. 19(2), 3700407 (2013).
[Crossref]

S. Manipatruni, M. Lipson, and I. A. Young, “Device scaling considerations for nanophotonic CMOS global interconnects,” IEEE J. Sel. Top. Quantum Electron. 19(2), 8200109 (2013).
[Crossref]

IEEE Photonics Technol. Lett. (1)

X. Zhu, K. Padmaraju, L. Luo, S. Yang, M. Glick, R. Dutt, M. Lipson, and K. Bergman, “Fast wavelength locking of a microring resonator,” IEEE Photonics Technol. Lett. 26(23), 2365–2368 (2014).
[Crossref]

IEEE Trans. Nucl. Sci. (1)

R. Giordano and A. Aloisio, “Fixed-latency, multi-gigabit serial links with xilinx FPGAs,” IEEE Trans. Nucl. Sci. 58(1), 194–201 (2011).
[Crossref]

IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (1)

Y. Audzevich, P. M. Watts, A. West, A. Mujumdar, S. W. Moore, and A. W. Moore, “Power optimized transceivers for future switched networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2081–2092 (2014).

J. Lightwave Technol. (1)

Opt. Express (1)

Other (18)

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. S. Williams, and K. Yelick, “Exascale computing study: technology challenges in achieving exascale systems,” Dep. CSE, Univ. Notre Dane, IN, USA, Rep. TR-2008–13, Sept. 2008.

B. Jacob, S. W. Ng, and D. T. Wang, “DRAM memory system organization,” in Memory System: Cache, DRAM, Disk, C. Glaser, P. Gottehrer, N. McFadden, and K. Honjo, eds. (Morgan Kaufmann, 2008), pp. 409–424.

S. Beamer, C. Sun, Y. J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, “Re-architecting DRAM memory systems with monolithically integrated silicon photonics,” in Proceedings of International Symposium on Computer Architecture, (ASSOC COMPUTING MACHINERY, 2010), pp. 129–140.
[Crossref]

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, “Corona: system implications of emerging nanophotonic technology,” in Proceedings of International Symposium on Computer Architecture (IEEE, 2008), pp. 153–164.
[Crossref]

H. Byun, I. Joe, S. Kim, K. Lee, S. Hong, H. Ji, J. Pyo, K. Cho, S. Kim, S. Suh, Y. Shin, S. Choi, J. Kim, S. Han, B. Lee, K. Na, D. Shin, K. Ha, Y. Park, K. Kim, J. Choi, T. Jeong, S. Hyun, J. Kim, H. Yoon, J. Nam, H. Kwon, H. Lee, J. Choi, J. Choi, and C. Chung, “FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects,” in Proceedings of IEEE Conference on Group IV Photonics (IEEE, 2013), pp. 5–6.
[Crossref]

K. Lee, D. J. Shin, H. Ji, K. W. Na, S. G. Kim, J. K. Bok, Y. S. You, S. S. Kim, I. S. Joe, S. D. Suh, J. H. Pyo, Y. H. Shin, K. H. Ha, Y. D. Park, and C. H. Chung, “10Gb/s silicon modulator based on bulk-silicon platform for DRAM optical interface,” in Proceedings of Conference on Optical Fiber Communication and Exposition and the National Fiber Optic Engineers Conference (OPTICAL SOC AMERICA, 2011), pp. 1–3.
[Crossref]

D. Brunina, X. Zhu, K. Padmaraju, C. Long, M. Lipson, and K. Bergman, “10-Gb/s WDM optically-connected memory system using silicon microring modulators,” in Proceedings of Conference and Exhibition on Optical Communications (IEEE, 2012), pp. 1–3.
[Crossref]

X. Yuan, “Future memory and interconnect technologies,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (IEEE, 2013), pp. 964–969.

C. Chen, T. Zhang, P. Contu, J. Klamkin, A. K. Coskun, and A. Joshi, “Sharing and placement of on-chip laser sources in silicon-photonic NoCs,” in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (IEEE, 2014), pp. 88–95.
[Crossref]

Z. Su, E. Timurdogan, J. Sun, M. Moresco, G. Leake, D. Coolbaugh, and M. R. Watts, “An on-chip partial drop wavelength selective broadcast network,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2014), pp.1–2.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

J. Hestness and S. W. Keckler, “Netrace: dependency-tracking traces for efficient network-on-chip experimentation,” Technical Report TR-10–11, The University of Texas at Austin, Department of Computer Science, May 2011.

C. Bienia and K. Li, “Fidelity and scaling of the PARSEC benchmark inputs,” in Proceedings of IEEE International Symposium on Workload Characterization (IEEE, 2010), pp. 1–10.
[Crossref]

A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, “High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip,” in Proceedings of Conference on Lasers and Electro-Optics (IEEE, 2011), pp. 1–2.
[Crossref]

R. Hendry, D. Nikolova, S. Rumley, and K. Bergman, “Modeling and evaluation of chip-to-chip scale silicon photonic networks,” in Proceedings of 2014 IEEE 22nd Annual Symposium on High-Performance Interconnects (IEEE, 2014), pp. 1–8.
[Crossref]

G. Li, X. Zheng, J. Lexau, Y. Luo, H. Thacker, P. Dong, S. Liao, D. Feng, D. Zheng, R. Shafiiha, M. Asghari, J. Yao, J. Shi, P. Amberg, N. Pinckney, K. Raj, R. Ho, J. Cunningham, and A. V. Krishnamoorthy, “Ultralow-power high-performance Si photonic transmitter,” inProceedings of Conference on Optical Fiber Communication and collocated National Fiber Optic Engineers (IEEE, 2010), pp. 1–3.

E. E. Hussein, S. Safwat, M. Ghoneima, and Y. Ismail, “A new signaling technique for a low power on-chip SerDes transceivers,” in Proceedings of International Conference on Energy Aware Computing (IEEE, 2010), pp. 1–2.
[Crossref]

K. Bergman, G. Hendry, P. Hargrove, J. Shalf, B. Jacob, K. S. Hemmert, A. Rodrigues, and D. Resnick, “Let there be light! The future of memory systems is photonics and 3D stacking,” In Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (ACM, 2011), pp. 43–48.

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Figures (10)

Fig. 1
Fig. 1 System with traditional electronic bus-based core-to-memory communication network. Only one rank can be accessed at one time.
Fig. 2
Fig. 2 An example of the proposed core-to-memory interconnection network. This network connects 64 cores with 4 ranks. (a) The layout of the core-to-memory communication network, cores and ranks. Three-dimensional integration and deposited silicon photonics technology are used. (b) A more detailed structure of the proposed network, including the locations of MRs and the wavelength assignment.
Fig. 3
Fig. 3 (a) The interface structures of a core and a rank. (b) Comparison of the proposed distributed pipeline-like MC and the traditional centralized MC, and the timing diagram of transmission of two transactions from one core to two ranks using two kinds of MC design. (c) Timing flowchart of transactions transmission. (d) Timing flowchart of the control packets.
Fig. 4
Fig. 4 Comparison of total return transactions from memory normalized to the electronic interconnect baseline on a 64-core system with three different configurations.
Fig. 5
Fig. 5 Comparison of average core-to-memory communication bandwidths normalized to the electronic interconnect baseline on 64-core system with three different configurations.
Fig. 6
Fig. 6 The procedure of logic address translation. (a) The 8-rank case translation procedure. (b) The 4-rank case address translation.
Fig. 7
Fig. 7 Comparison of average core-to-memory communication latencies normalized to the optical interconnect (8 ranks are optically linked with cores) baseline on 64-core system with three different configurations.
Fig. 8
Fig. 8 Simulation results of distributions of return transactions over latency when running x264 application from PARSEC benchmark under three different configurations.
Fig. 9
Fig. 9 Power analysis model of optical communication.
Fig. 10
Fig. 10 Tradeoff between energy cost and bandwidth.of the proposed network. (a) Benchmarks except vips. (b) Vips benchmark.

Tables (3)

Tables Icon

Table 1 Simulation Configurations of Two Comparison System

Tables Icon

Table 2 Parameters of Optical Devices

Tables Icon

Table 3 Stacked DRAM Design Components

Equations (8)

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[ λ 1 λ 2 λ 3 λ 64 λ 2 λ 3 λ 4 λ 1 λ 3 λ 4 λ 5 λ 2 λ 4 λ 5 λ 6 λ 3 ]
Grou p i ={Cor e n k i ,Cor e n k i+1 ,...,Cor e n k i+ n k 1 }, i=0 k1 Grou p i ={ Cor e 0 ,Cor e 1 ,...,Cor e n1 } .
[ λ 0,0 λ 0,1 λ 0,2 λ 0,k1 λ 1,0 λ 1,1 λ 1,2 λ 1,k1 λ m1,0 λ m1,1 λ m1,2 λ m1,k1 ]
λ u,v ={ λ u+v+1 , u+vk1 λ (u+v+1)mod(k) , u+v>k1 .
E total = E optical + E memory .
P laser = 10 ( S det + L mod + L link + L det ) 10 η laser (mW),
L link = L propagation + L drop + L through + L bend + L crossing ,
E erergyperbit =[ V 2 ×( C bl + C cell + C wl /bA)× O cmd + E TSV ]× O ECC .

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