Abstract

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

© 2014 Optical Society of America

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  12. L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
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    [CrossRef]
  22. W.-K. Huang, Y.-C. Liu, Y.-M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,” IEEE Photonics Technol. Lett. 19(4), 197–199 (2007).
    [CrossRef]
  23. K. Iiyama, H. Takamatsu, T. Maruyama, “Hole-injection-type and electron-injection-type silicon avalanche photodiodes fabricated by standard 0.18-µm CMOS process,” IEEE Photonics Technol. Lett. 22(12), 932–934 (2010).
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    [CrossRef]
  26. M.-J. Lee, W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express 18(23), 24189–24194 (2010).
    [CrossRef] [PubMed]
  27. M.-J. Lee, W.-Y. Choi, “Area-dependent photodetection frequency response characterization of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Trans. Electron. Dev. 60(3), 998–1004 (2013).
    [CrossRef]
  28. M.-J. Lee, H. Rücker, W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron. Device Lett. 33(1), 80–82 (2012).
    [CrossRef]

2013

M.-J. Lee, W.-Y. Choi, “Area-dependent photodetection frequency response characterization of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Trans. Electron. Dev. 60(3), 998–1004 (2013).
[CrossRef]

2012

M.-J. Lee, H. Rücker, W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron. Device Lett. 33(1), 80–82 (2012).
[CrossRef]

F. E. Doany, C. L. Schow, B. G. Lee, R. A. Budd, C. W. Baks, C. K. Tsang, J. U. Knickerbocker, R. Dangel, B. Chan, H. Lin, C. Carver, J. Huang, J. Berry, D. Bajkowski, F. Libsch, J. A. Kash, “Terabit/s-class optical PCB links incorporating 360-Gb/s bidirectional 850 nm parallel optical transceivers,” J. Lightwave Technol. 30(4), 560–571 (2012).
[CrossRef]

P. Duan, O. Raz, B. E. Smalbrugge, J. Duis, H. J. S. Dorren, “A novel 3D stacking method for Opto-electronic dies on CMOS ICs,” Opt. Express 20(26), B386–B392 (2012).
[CrossRef] [PubMed]

J.-S. Youn, M.-J. Lee, K.-Y. Park, W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

2011

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-µm CMOS technology,” IEEE J. Solid State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

C. L. Schow, F. E. Doany, A. V. Rylyakov, B. G. Lee, C. V. Jahnes, Y. H. Kwark, C. W. Baks, D. M. Kuchta, J. A. Kash, “A 24-channel, 300 Gb/s, 8.2 pJ/bit, full-duplex fiber-coupled optical transceiver module based on a single “holey” CMOS IC,” J. Lightwave Technol. 29(4), 542–553 (2011).
[CrossRef]

2010

M.-J. Lee, W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express 18(23), 24189–24194 (2010).
[CrossRef] [PubMed]

K. Iiyama, H. Takamatsu, T. Maruyama, “Hole-injection-type and electron-injection-type silicon avalanche photodiodes fabricated by standard 0.18-µm CMOS process,” IEEE Photonics Technol. Lett. 22(12), 932–934 (2010).
[CrossRef]

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

D. Lee, J. Han, G. Han, S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slop-detection adaptive equalizer,” IEEE J. Solid State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

T. S. Kao, F. A. Musa, A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I, Reg. Pap. 57(11), 2844–2857 (2010).

2009

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

F. Tavernier, M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

2007

W.-K. Huang, Y.-C. Liu, Y.-M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,” IEEE Photonics Technol. Lett. 19(4), 197–199 (2007).
[CrossRef]

2006

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

B. Jalali, S. Fathpour, “Silicon photonics,” J. Lightwave Technol. 24(12), 4600–4615 (2006).
[CrossRef]

2005

S. Radovanovic, A.-J. Annema, B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid State Circuits 40(8), 1706–1717 (2005).
[CrossRef]

Annema, A.-J.

S. Radovanovic, A.-J. Annema, B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid State Circuits 40(8), 1706–1717 (2005).
[CrossRef]

Bajkowski, D.

Baks, C. W.

Bamiedakis, N.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

Barkai, A.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Beals, J.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

Bellec, M.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Berry, J.

Block, B. A.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Budd, R. A.

Cárdenas, D.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Carusone, A. C.

T. S. Kao, F. A. Musa, A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I, Reg. Pap. 57(11), 2844–2857 (2010).

Carver, C.

Chan, B.

Chang, P. L. D.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Chang, W.-H.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Chang, Y.-W.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-µm CMOS technology,” IEEE J. Solid State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

Charbonnier, B.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Chen, G.-Y.

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

Chen, W.-Z.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-µm CMOS technology,” IEEE J. Solid State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

W.-Z. Chen, S.-H. Huang, “A 2.5 Gbps CMOS fully integrated optical receiver with lateral PIN detector,” in Proc. Custom Integrated Circuits Conf. 293–296 (2007).
[CrossRef]

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Chiu, C.-F.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Choi, W.-Y.

M.-J. Lee, W.-Y. Choi, “Area-dependent photodetection frequency response characterization of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Trans. Electron. Dev. 60(3), 998–1004 (2013).
[CrossRef]

J.-S. Youn, M.-J. Lee, K.-Y. Park, W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

M.-J. Lee, H. Rücker, W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron. Device Lett. 33(1), 80–82 (2012).
[CrossRef]

M.-J. Lee, W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express 18(23), 24189–24194 (2010).
[CrossRef] [PubMed]

Chou, F.-P.

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

Clapp, T. V.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

Cohen, O.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Cohen, R.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Dangel, R.

DeGroot, J. V.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

Dellmann, L.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Despont, M.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Doany, F. E.

Dorren, H. J. S.

Drechsler, U.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Duan, P.

Duis, J.

Evanno, N.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Fathpour, S.

Gaudino, R.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Guignard, P.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Gunn, C.

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

Han, G.

D. Lee, J. Han, G. Han, S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slop-detection adaptive equalizer,” IEEE J. Solid State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Han, J.

D. Lee, J. Han, G. Han, S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slop-detection adaptive equalizer,” IEEE J. Solid State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Hsin, Y.-M.

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

W.-K. Huang, Y.-C. Liu, Y.-M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,” IEEE Photonics Technol. Lett. 19(4), 197–199 (2007).
[CrossRef]

Huang, J.

Huang, S.-H.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-µm CMOS technology,” IEEE J. Solid State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

W.-Z. Chen, S.-H. Huang, “A 2.5 Gbps CMOS fully integrated optical receiver with lateral PIN detector,” in Proc. Custom Integrated Circuits Conf. 293–296 (2007).
[CrossRef]

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Huang, W.-K.

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

W.-K. Huang, Y.-C. Liu, Y.-M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,” IEEE Photonics Technol. Lett. 19(4), 197–199 (2007).
[CrossRef]

Huang, Y.-T.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-µm CMOS technology,” IEEE J. Solid State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Iiyama, K.

K. Iiyama, H. Takamatsu, T. Maruyama, “Hole-injection-type and electron-injection-type silicon avalanche photodiodes fabricated by standard 0.18-µm CMOS process,” IEEE Photonics Technol. Lett. 22(12), 932–934 (2010).
[CrossRef]

Izhaky, N.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Jäger, D.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Jahnes, C. V.

Jalali, B.

Juang, Y.-Z.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Kao, T. S.

T. S. Kao, F. A. Musa, A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I, Reg. Pap. 57(11), 2844–2857 (2010).

Kash, J. A.

Kern, A. M.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Knickerbocker, J. U.

Koehl, S.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Kuchta, D. M.

Kwark, Y. H.

Lee, B. G.

Lee, D.

D. Lee, J. Han, G. Han, S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slop-detection adaptive equalizer,” IEEE J. Solid State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Lee, M.-J.

M.-J. Lee, W.-Y. Choi, “Area-dependent photodetection frequency response characterization of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Trans. Electron. Dev. 60(3), 998–1004 (2013).
[CrossRef]

M.-J. Lee, H. Rücker, W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron. Device Lett. 33(1), 80–82 (2012).
[CrossRef]

J.-S. Youn, M.-J. Lee, K.-Y. Park, W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

M.-J. Lee, W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express 18(23), 24189–24194 (2010).
[CrossRef] [PubMed]

Liao, J. T. S.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Libsch, F.

Lin, H.

Liu, C.-C.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Liu, Y.-C.

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

W.-K. Huang, Y.-C. Liu, Y.-M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,” IEEE Photonics Technol. Lett. 19(4), 197–199 (2007).
[CrossRef]

Maruyama, T.

K. Iiyama, H. Takamatsu, T. Maruyama, “Hole-injection-type and electron-injection-type silicon avalanche photodiodes fabricated by standard 0.18-µm CMOS process,” IEEE Photonics Technol. Lett. 22(12), 932–934 (2010).
[CrossRef]

Meyer, S.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

Mohammed, E.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Möllers, I.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Morf, T.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Morse, M. T.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Musa, F. A.

T. S. Kao, F. A. Musa, A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I, Reg. Pap. 57(11), 2844–2857 (2010).

Nauta, B.

S. Radovanovic, A.-J. Annema, B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid State Circuits 40(8), 1706–1717 (2005).
[CrossRef]

Palermo, S.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Paniccia, M. J.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Park, K.-Y.

J.-S. Youn, M.-J. Lee, K.-Y. Park, W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

Park, S. M.

D. Lee, J. Han, G. Han, S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slop-detection adaptive equalizer,” IEEE J. Solid State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Penty, R. V.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

Pizzinat, A.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

Radovanovic, S.

S. Radovanovic, A.-J. Annema, B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid State Circuits 40(8), 1706–1717 (2005).
[CrossRef]

Raz, O.

Reshotko, M. R.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

Rothuizen, H.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Rubin, D.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Rücker, H.

M.-J. Lee, H. Rücker, W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron. Device Lett. 33(1), 80–82 (2012).
[CrossRef]

Rylyakov, A. V.

Sarid, G.

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

Schow, C. L.

Smalbrugge, B. E.

Soref, R.

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

Steyaert, M. S. J.

F. Tavernier, M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

Stutz, R.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Takamatsu, H.

K. Iiyama, H. Takamatsu, T. Maruyama, “Hole-injection-type and electron-injection-type silicon avalanche photodiodes fabricated by standard 0.18-µm CMOS process,” IEEE Photonics Technol. Lett. 22(12), 932–934 (2010).
[CrossRef]

Tavernier, F.

F. Tavernier, M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

Tsang, C. K.

Wang, C.-W.

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

Weiss, J.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

White, I. H.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

Wu, G.-W.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

Youn, J.-S.

J.-S. Youn, M.-J. Lee, K.-Y. Park, W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

Young, I. A.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

IEEE Commun. Mag.

R. Gaudino, D. Cárdenas, M. Bellec, B. Charbonnier, N. Evanno, P. Guignard, S. Meyer, A. Pizzinat, I. Möllers, D. Jäger, “Perspective in next-generation home networks-Toward optical solutions,” IEEE Commun. Mag. 48(2), 39–47 (2010).
[CrossRef]

IEEE Electron. Device Lett.

M.-J. Lee, H. Rücker, W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron. Device Lett. 33(1), 80–82 (2012).
[CrossRef]

IEEE J. Quantum Electron.

N. Bamiedakis, J. Beals, R. V. Penty, I. H. White, J. V. DeGroot, T. V. Clapp, “Cost-effective multimode polymer waveguides for high-speed on-board optical interconnect,” IEEE J. Quantum Electron. 45(4), 415–424 (2009).
[CrossRef]

J.-S. Youn, M.-J. Lee, K.-Y. Park, W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron.

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

N. Izhaky, M. T. Morse, S. Koehl, O. Cohen, D. Rubin, A. Barkai, G. Sarid, R. Cohen, M. J. Paniccia, “Development of CMOS-compatible integrated silicon photonics devices,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1688–1698 (2006).
[CrossRef]

F.-P. Chou, G.-Y. Chen, C.-W. Wang, Y.-C. Liu, W.-K. Huang, Y.-M. Hsin, “Silicon photodiodes in standard CMOS technology,” IEEE J. Sel. Top. Quantum Electron. 17(3), 730–740 (2011).
[CrossRef]

IEEE J. Solid State Circuits

F. Tavernier, M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid State Circuits 45(1), 235–248 (2010).
[CrossRef]

S. Radovanovic, A.-J. Annema, B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid State Circuits 40(8), 1706–1717 (2005).
[CrossRef]

D. Lee, J. Han, G. Han, S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slop-detection adaptive equalizer,” IEEE J. Solid State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-µm CMOS technology,” IEEE J. Solid State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

IEEE Micro

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

IEEE Photonics Technol. Lett.

W.-K. Huang, Y.-C. Liu, Y.-M. Hsin, “A high-speed and high-responsivity photodiode in standard CMOS technology,” IEEE Photonics Technol. Lett. 19(4), 197–199 (2007).
[CrossRef]

K. Iiyama, H. Takamatsu, T. Maruyama, “Hole-injection-type and electron-injection-type silicon avalanche photodiodes fabricated by standard 0.18-µm CMOS process,” IEEE Photonics Technol. Lett. 22(12), 932–934 (2010).
[CrossRef]

IEEE Trans. Circuits Syst. I, Reg. Pap.

T. S. Kao, F. A. Musa, A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I, Reg. Pap. 57(11), 2844–2857 (2010).

IEEE Trans. Electron. Dev.

M.-J. Lee, W.-Y. Choi, “Area-dependent photodetection frequency response characterization of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Trans. Electron. Dev. 60(3), 998–1004 (2013).
[CrossRef]

J. Lightwave Technol.

Microelectron. Eng.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng. 87(5–8), 1210–1212 (2010).
[CrossRef]

Opt. Express

Proc. IEEE

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

Other

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proc. IEEE Asian Solid-State Circuits Conf. 396–399 (2007).

O. Strobel, R. Rejeb, and J. Lubkoll, “Communication in automotive systems: principles, limits and new trends for vehicles, airplanes and vessels,” Int. Conf. Transparent Opt. Netw. 1–6 (2010).
[CrossRef]

W.-Z. Chen, S.-H. Huang, “A 2.5 Gbps CMOS fully integrated optical receiver with lateral PIN detector,” in Proc. Custom Integrated Circuits Conf. 293–296 (2007).
[CrossRef]

H. Zimmermann, Integrated Silicon Optoelectronics, 2nd ed. (Springer, 2009).

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Figures (7)

Fig. 1
Fig. 1

Structure of the fabricated SM-APD.

Fig. 2
Fig. 2

(a) CMOS-Rx based on the proposed SM-APD. (b) Chip microphotograph.

Fig. 3
Fig. 3

Experimental setup.

Fig. 4
Fig. 4

Responsivity and avalanche gain of the fabricated SM-APD as a function of the reverse bias voltage.

Fig. 5
Fig. 5

(a) Measured photodetection frequency responses of the SM-APD. (b) Normalized photodetection frequency responses of the SM-APD. Hollow circles represent measured data, and solid lines represent fitted curves.

Fig. 6
Fig. 6

(a) Normalized photodetection frequency response of the CMOS-Rx based on the SM-APD and (b) measured BER performance versus incident optical power and eye diagram for 12.5-Gb/s optical data.

Fig. 7
Fig. 7

Performance comparison of CMOS-Rxs in terms of data rate and power efficiency.

Tables (1)

Tables Icon

Table 1 Performance Summary and Comparison with other CMOS-Rxs

Metrics