Abstract

The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

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References

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  1. A. Vahdat, L. Hong, Z. Xiaoxue, and C. Johnson, “The emerging optical data center,” in conference of Optical Fiber Communication Conference and Exposition (OFC/NOFEC) 2011, pp. 1–3.
  2. H. Liu, C. F. Lam, and C. Johnson, “Scaling Optical Interconnects in Datacenter Networks, Opportunities and Challenges for WDM.” Google Inc, Moumtain view, CA.(2010). http://www.research.google.com/pubs/archive/36670.pdf .
  3. L. Peng, C. Qiao, W. Tang, and C. Youn, “Cube-Based Intra-Datacenter Networks with LOBS-HC,” in international conference on communications (ICC) 2011, pp 1–6.
  4. C. Albrecht, J. Foag, R. Koch, E. Maehle, and T. Pionteck, “DynaCORE—Dynamically Reconfigurable Coprocessor for Network Processors,” (Dynamically Reconfigurable Systems, 335–354, 2010).
  5. M. Hubner, L. Braun, D. Gohringer, and J. Becker, “Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems,” International Symposium on Parallel and Distributed Processing (IPDPS) 2008. pp. 1–6.
  6. G. S. Zervas, J. Triay, N. Amaya, Y. Qin, C. Cervelló-Pastor, and D. Simeonidou, “Time Shared Optical Network (TSON): a novel metro architecture for flexible multi-granular services,” Opt. Express19(26), B509–B514 (2011).
    [CrossRef] [PubMed]
  7. N. Amaya, G. S. Zervas, B. R. Rofoee, M. Irfan, Y. Qin, and D. Simeonidou, “Field trial of a 1.5 Tb/s adaptive and gridless OXC supporting elastic 1000-fold bandwidth granularity,” in European Conference and Exhibition on Optical Communication (ECOC), 2011, pp.1–3.

2011

Amaya, N.

Cervell├│-Pastor, C.

Qin, Y.

Simeonidou, D.

Triay, J.

Zervas, G. S.

Opt. Express

Other

N. Amaya, G. S. Zervas, B. R. Rofoee, M. Irfan, Y. Qin, and D. Simeonidou, “Field trial of a 1.5 Tb/s adaptive and gridless OXC supporting elastic 1000-fold bandwidth granularity,” in European Conference and Exhibition on Optical Communication (ECOC), 2011, pp.1–3.

A. Vahdat, L. Hong, Z. Xiaoxue, and C. Johnson, “The emerging optical data center,” in conference of Optical Fiber Communication Conference and Exposition (OFC/NOFEC) 2011, pp. 1–3.

H. Liu, C. F. Lam, and C. Johnson, “Scaling Optical Interconnects in Datacenter Networks, Opportunities and Challenges for WDM.” Google Inc, Moumtain view, CA.(2010). http://www.research.google.com/pubs/archive/36670.pdf .

L. Peng, C. Qiao, W. Tang, and C. Youn, “Cube-Based Intra-Datacenter Networks with LOBS-HC,” in international conference on communications (ICC) 2011, pp 1–6.

C. Albrecht, J. Foag, R. Koch, E. Maehle, and T. Pionteck, “DynaCORE—Dynamically Reconfigurable Coprocessor for Network Processors,” (Dynamically Reconfigurable Systems, 335–354, 2010).

M. Hubner, L. Braun, D. Gohringer, and J. Becker, “Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems,” International Symposium on Parallel and Distributed Processing (IPDPS) 2008. pp. 1–6.

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Figures (8)

Fig. 1
Fig. 1

(a) legacy ToR in Fat-Tree intra-datacenter network architecture. (b) Transparent network on-chip and off-chip to replace the legacy architecture. (c) Network off-chip where optical components are selected for Ethernet or TSON connectivity paradigms. (d) FPGA based Network on-chip implementation with modules attached to an electronic back plane.

Fig. 2
Fig. 2

(a) network off-chip for optical transport of broadcast and select delivering EoWSON(b) network on-chip for building TSON and Ethernet interfaces (c) network off-chip for TSON operation

Fig. 3
Fig. 3

FPGA-based TSON-Ethernet switching NoC results. (a) Throughput. (b) Ethernet/TSON latency.

Fig. 4
Fig. 4

FPGA-based TSON-Ethernet NoC results. (a) switch-over. (b) Tx/Rx frames.

Fig. 5
Fig. 5

1Gbps slice allocation patterns. (a) P1: contiguous allocation. (b) P2: distributed allocation.

Fig. 6
Fig. 6

FPGA-based TSON latency for different time slice allocation. (a) for 64 Byte Ethernet frame size, (b) for 1500 Byte Ethernet frame size.

Fig. 7
Fig. 7

FPGA-based TSON jitter for 64 Byte Ethernet frames with different time slice allocation patterns. (a) time slice allocation pattern 1, (b) time slice allocation pattern 2.

Fig. 8
Fig. 8

FPGA-based TSON jitter for 64 Byte Ethernet frames with different time slice allocation patterns. (a) time slice allocation patterns 1, (b) time slice allocation patterns 2.

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