Abstract

We have proposed and demonstrated a novel method to measure depths of through silicon vias (TSVs) at high speed. TSVs are fine and deep holes fabricated in silicon wafers for 3D semiconductors; they are used for electrical connections between vertically stacked wafers. Because the high-aspect ratio hole of the TSV makes it difficult for light to reach the bottom surface, conventional optical methods using visible lights cannot determine the depth value. By adopting an optical comb of a femtosecond pulse laser in the infra-red range as a light source, the depths of TSVs having aspect ratio of about 7 were measured. This measurement was done at high speed based on spectral resolved interferometry. The proposed method is expected to be an alternative method for depth inspection of TSVs.

© 2012 OSA

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References

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  1. M. Born and E. Wolf, “Elements of the theory of diffraction,” in Principles of Optics (Cambridge University Press, Cambridge, UK, 2006).
  2. K. R. Chen, “Focusing of light beyond the diffraction limit of half the wavelength,” Opt. Lett. 35(22), 3763–3765 (2010).
    [CrossRef] [PubMed]
  3. S. Kühne and C. Hierold, “Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias,” J. Micromech. Microeng. 21(8), 085032 (2011).
    [CrossRef]
  4. L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
    [CrossRef]
  5. M. Esashi, “Wafer level packaging of MEMS,” J. Micromech. Microeng. 18(7), 073001 (2008).
    [CrossRef]
  6. J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
    [CrossRef]
  7. C. Song, Z. Wang, and L. Liu, “Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias,” Microelectron. Eng. 87(3), 510–513 (2010).
    [CrossRef]
  8. J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
    [CrossRef]
  9. Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
    [CrossRef]
  10. L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).
  11. J. Jin, J. W. Kim, C.-S. Kang, J.-A. Kim, and T. B. Eom, “Thickness and refractive index measurement of a silicon wafer based on an optical comb,” Opt. Express 18(17), 18339–18346 (2010).
    [CrossRef] [PubMed]
  12. J. Jin, Y.-J. Kim, Y. Kim, S.-W. Kim, and C.-S. Kang, “Absolute length calibration of gauge blocks using optical comb of a femtosecond pulse laser,” Opt. Express 14(13), 5968–5974 (2006).
    [CrossRef] [PubMed]
  13. ISO, “ISO-5436-1 Geometrical product specifications (GPS) - Surface texture: Profile method; Measurement standards-Part 1: Material measures” (2000).
  14. ISO, “ISO-4287 Geometrical product specifications (GPS) – Surface texture: Profile method-terms, Definitions and surface texture parameters” (1997).

2011 (4)

S. Kühne and C. Hierold, “Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias,” J. Micromech. Microeng. 21(8), 085032 (2011).
[CrossRef]

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
[CrossRef]

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

2010 (4)

J. Jin, J. W. Kim, C.-S. Kang, J.-A. Kim, and T. B. Eom, “Thickness and refractive index measurement of a silicon wafer based on an optical comb,” Opt. Express 18(17), 18339–18346 (2010).
[CrossRef] [PubMed]

K. R. Chen, “Focusing of light beyond the diffraction limit of half the wavelength,” Opt. Lett. 35(22), 3763–3765 (2010).
[CrossRef] [PubMed]

C. Song, Z. Wang, and L. Liu, “Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias,” Microelectron. Eng. 87(3), 510–513 (2010).
[CrossRef]

L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
[CrossRef]

2008 (1)

M. Esashi, “Wafer level packaging of MEMS,” J. Micromech. Microeng. 18(7), 073001 (2008).
[CrossRef]

2006 (1)

Aelst, J. V.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Ammel, A. V.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Arkalgud, S.

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

Armini, S.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Beyne, E.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Chen, K. R.

Chen, L.-S.

J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
[CrossRef]

Cheng, H.-C.

L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
[CrossRef]

Chien, C.-W.

L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
[CrossRef]

Coenen, J.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Dehaene, W.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Diebold, A. C.

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

Eom, T. B.

Esashi, M.

M. Esashi, “Wafer level packaging of MEMS,” J. Micromech. Microeng. 18(7), 073001 (2008).
[CrossRef]

Fujimori, Y.

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

Hierold, C.

S. Kühne and C. Hierold, “Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias,” J. Micromech. Microeng. 21(8), 085032 (2011).
[CrossRef]

Huyghebaert, C.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Inoue, T.

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

Jin, J.

Kang, C.-S.

Katti, G.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Kim, J. W.

Kim, J.-A.

Kim, S.-W.

Kim, Y.

Kim, Y.-J.

Kong, L.

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

Krueger, R.

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

Kudo, Y.

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

Kühne, S.

S. Kühne and C. Hierold, “Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias,” J. Micromech. Microeng. 21(8), 085032 (2011).
[CrossRef]

Lay, Y.-J.

J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
[CrossRef]

Lin, C.-T.

L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
[CrossRef]

Lin, L.-Y.

J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
[CrossRef]

Liu, L.

C. Song, Z. Wang, and L. Liu, “Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias,” Microelectron. Eng. 87(3), 510–513 (2010).
[CrossRef]

Okamoto, K.

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

Olmen, J. V.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Rudack, A. C.

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

Shen, L.-C.

L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
[CrossRef]

Sleeckx, E.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Song, C.

C. Song, Z. Wang, and L. Liu, “Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias,” Microelectron. Eng. 87(3), 510–513 (2010).
[CrossRef]

Tang, J.-J.

J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
[CrossRef]

Travaly, Y.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Tsuto, T.

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

Vaes, J.

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

Wang, Z.

C. Song, Z. Wang, and L. Liu, “Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias,” Microelectron. Eng. 87(3), 510–513 (2010).
[CrossRef]

Zschech, E.

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

ECS Trans. (1)

J.-J. Tang, Y.-J. Lay, L.-S. Chen, and L.-Y. Lin, “TSV/3DIC profile metrology based on infrared microscope image,” ECS Trans. 34, 937–942 (2011).
[CrossRef]

J. Micromech. Microeng. (2)

S. Kühne and C. Hierold, “Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias,” J. Micromech. Microeng. 21(8), 085032 (2011).
[CrossRef]

M. Esashi, “Wafer level packaging of MEMS,” J. Micromech. Microeng. 18(7), 073001 (2008).
[CrossRef]

Microelectron. Eng. (3)

J. V. Olmen, C. Huyghebaert, J. Coenen, J. V. Aelst, E. Sleeckx, A. V. Ammel, S. Armini, G. Katti, J. Vaes, W. Dehaene, E. Beyne, and Y. Travaly, “Integration challenges of copper through silicon via (TSV) metallization for 3D-stacked IC integration,” Microelectron. Eng. 88(5), 745–748 (2011).
[CrossRef]

C. Song, Z. Wang, and L. Liu, “Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias,” Microelectron. Eng. 87(3), 510–513 (2010).
[CrossRef]

L. Kong, A. C. Rudack, R. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-interconnect: visualization of extrusion and voids induced in copper-filled through-silicon vias (TSVs) at various temperatures using X-ray microscopy,” Microelectron. Eng. (to be published).

Microelectron. Reliab. (1)

L.-C. Shen, C.-W. Chien, H.-C. Cheng, and C.-T. Lin, “Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection,” Microelectron. Reliab. 50(4), 489–497 (2010).
[CrossRef]

Opt. Express (2)

Opt. Lett. (1)

Proc. SPIE (1)

Y. Fujimori, T. Tsuto, Y. Kudo, T. Inoue, and K. Okamoto, “A new methodology for TSV array inspection,” Proc. SPIE 7971, 79710I (2011).
[CrossRef]

Other (3)

M. Born and E. Wolf, “Elements of the theory of diffraction,” in Principles of Optics (Cambridge University Press, Cambridge, UK, 2006).

ISO, “ISO-5436-1 Geometrical product specifications (GPS) - Surface texture: Profile method; Measurement standards-Part 1: Material measures” (2000).

ISO, “ISO-4287 Geometrical product specifications (GPS) – Surface texture: Profile method-terms, Definitions and surface texture parameters” (1997).

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Figures (5)

Fig. 1
Fig. 1

Spectrum of the femtosecond pulse laser: (a) full spectrum of the femtosceond pulse laser and (b) the optical comb of the femtosecond pulse laser with a Fabry-Perot etalon having a free spectral range of 25 GHz.

Fig. 2
Fig. 2

Optical layout of the TSV depth measurement system (FPE: Fabry-Perot etalon, BS: beam splitter, OL: objective lens, CL: collimation lens, FL: focusing lens, C: optical coupler, PD: photo-detector, OSA: optical spectrum analyzer).

Fig. 3
Fig. 3

Measurement sample having TSVs: (a) top view of the TSVs (b) cross-section view of the TSV measured by SEM.

Fig. 4
Fig. 4

Fourier transform of the interference spectrum at: (a) the top surface; (b) the near edges; (c) the bottom surface of the TSV.

Fig. 5
Fig. 5

Measurement results. (a) profile of the TSV obtained by the suggested method. (The scale on each axis is not equal.). (b) three-dimensional profile of the TSV.

Tables (1)

Tables Icon

Table 1 Measurement Results of the TSV Depths (unit: μm)

Equations (5)

Equations on this page are rendered with MathJax. Learn more.

I(f,L)= I 0 (f)( 1+cos( c Lf ) )= I 0 (f)( 1+cosφ( f,L ) )
I(t)= I 0 (t)( 1+ 1 2 δ( tF )+ 1 2 δ( t+F ) )
φ(f,L)=Im{ ln( I'(f) ) }
L= c dφ df
z(x)=αx+β+hδ

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