Abstract

A high speed, high density and potentially low cost solution for realizing a compact transceiver module is presented in this paper. It is based on directly bonding an Opto-electronic die on top of CMOS IC chip and creating a photoresist ramp to bridge the big step (around 220μm) from Opto-electronic pads to CMOS IC pads. The required electrical connection between them is realized lithographically with a process than can be scaled to full wafer production. A 12-channel transmitter based on the technique was fabricated and test shows good performance up to 12.5 Gb/s/ch.

© 2012 OSA

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References

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  1. D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE88(6), 728–749 (2000).
    [CrossRef]
  2. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009).
    [CrossRef]
  3. H. J. S. Dorren, P. Duan, O. Raz, and R. P. Luijten, “Fundamental bounds for photonic interconnects,” 13th International Conference on Transparent Optical Networks (ICTON, Stockholm, 2011), paper Mo.C1.1.
  4. L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
    [CrossRef]
  5. C. L. Schow, F. E. Doany, A. V. Rylyakov, B. G. Lee, C. V. Jahnes, Y. H. Kwark, C. W. Baks, D. M. Kuchta, and J. A. Kash, “A 24-Channel, 300 Gb/s, 8.2 pJ/bit, full-duplex fiber-coupled optical transceiver module based on a single “Holey” CMOS IC,” J. Lightwave Technol.29(4), 542–553 (2011).
    [CrossRef]
  6. F. E. Doany, B. G. Lee, A. V. Rylyakov, D. M. Kuchta, C. Baks, C. Jahnes, F. Libsch, and C. L. Schow, “Terabit/sec VCSEL-based parallel optical module based on Holey CMOS transceiver IC”. In Proceeding of the Optical Fiber communication conference (OFC/NFOEC, Los Angeles, 2012), PDP5D.9.
  7. P. Duan, O. Raz, B. E. Smalbrugge, J. Duis, and H. J. S. Dorren, “Chip-to-chip interconnects based on 3D stacking of opto-electrical dies on Si, ” in the Proc. SPIE. 8267, Optoelectronic Interconnects XII, 82670U (San Francisco, 2012).

2011 (1)

2010 (1)

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

2009 (1)

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009).
[CrossRef]

2000 (1)

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE88(6), 728–749 (2000).
[CrossRef]

Baks, C. W.

Dellmann, L.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Despont, M.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Doany, F. E.

Drechsler, U.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Jahnes, C. V.

Kash, J. A.

Kuchta, D. M.

Kwark, Y. H.

Lee, B. G.

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009).
[CrossRef]

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE88(6), 728–749 (2000).
[CrossRef]

Morf, T.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Rothuizen, H.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Rylyakov, A. V.

Schow, C. L.

Stutz, R.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Weiss, J.

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

J. Lightwave Technol. (1)

Microelectron. Eng. (1)

L. Dellmann, U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont, “3D opto-electrical device stacking on CMOS,” Microelectron. Eng.87(5-8), 1210–1212 (2010).
[CrossRef]

Proc. IEEE (2)

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE88(6), 728–749 (2000).
[CrossRef]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE97(7), 1166–1185 (2009).
[CrossRef]

Other (3)

H. J. S. Dorren, P. Duan, O. Raz, and R. P. Luijten, “Fundamental bounds for photonic interconnects,” 13th International Conference on Transparent Optical Networks (ICTON, Stockholm, 2011), paper Mo.C1.1.

F. E. Doany, B. G. Lee, A. V. Rylyakov, D. M. Kuchta, C. Baks, C. Jahnes, F. Libsch, and C. L. Schow, “Terabit/sec VCSEL-based parallel optical module based on Holey CMOS transceiver IC”. In Proceeding of the Optical Fiber communication conference (OFC/NFOEC, Los Angeles, 2012), PDP5D.9.

P. Duan, O. Raz, B. E. Smalbrugge, J. Duis, and H. J. S. Dorren, “Chip-to-chip interconnects based on 3D stacking of opto-electrical dies on Si, ” in the Proc. SPIE. 8267, Optoelectronic Interconnects XII, 82670U (San Francisco, 2012).

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Figures (9)

Fig. 1
Fig. 1

(a) 3D stacking model demonstration. (b) 3D stacking single module chip artificial show based on VCSEL array and VCSEL CMOS driver.

Fig. 2
Fig. 2

VCSEL array bonding on the CMOS.

Fig. 3
Fig. 3

After reflow and seed layer.

Fig. 4
Fig. 4

SEM image of the lithography between VCSELs and CMOS driver IC (a). The lithographically defined metallization positions near the VCSEL array (b) or near VCSEL driver pads (c) respectively.

Fig. 5
Fig. 5

SEM image of the plating metal traces (a). The plating quality near the VCSEL array (b) or near VCSEL driver pads (c) respectively.

Fig. 6
Fig. 6

SEM image of the electrical path between VCSELs and CMOS driver IC (a). The plating quality near the VCSEL array (b) or near VCSEL driver pads (c) respectively.

Fig. 7
Fig. 7

I-V-P testing results.

Fig. 8
Fig. 8

S11 testing results.

Fig. 9
Fig. 9

(a) Eye diagram at 10 Gb/s. (b) Eye diagram at 12.5 Gb/s.

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