Abstract

In recent years, limitations in optical lithography have challenged the cost-effective manufacture of nano- and microelectronic chips. Spatially regular designs have been introduced to improve manufacturability. However, regular designed layouts typically require an interference step followed by a trim step. These multiple steps increase cost and reduce yield. In the present work, Pattern-Integrated Interference Lithography (PIIL) is introduced to address this problem. PIIL is the integration of interference lithography and superposed pattern mask imaging, combining the interference and the trim into a single-exposure step. Example PIIL implementations and experimental demonstrations are presented. The degrees of freedom associated with the source, pattern mask, and Fourier filter designs are described.

© 2012 OSA

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2012 (2)

G. M. Burrow, M. C. R. Leibovici, J. W. Kummer, and T. K. Gaylord, “Pattern-integrated interference lithography instrumentation,” Rev. Sci. Instrum.83(6), 063707 (2012).
[CrossRef] [PubMed]

G. M. Burrow, M. C. R. Leibovici, and T. K. Gaylord, “Pattern-integrated interference lithography: single-exposure fabrication of photonic-crystal structures,” Appl. Opt.51(18), 4028–4041 (2012).
[CrossRef] [PubMed]

2011 (1)

J. L. Stay, G. M. Burrow, and T. K. Gaylord, “Three-beam interference lithography methodology,” Rev. Sci. Instrum.82(2), 023115 (2011).
[CrossRef] [PubMed]

2009 (2)

J. L. Stay and T. K. Gaylord, “Conditions for primitive-lattice-vector-direction equal contrasts in four-beam-interference lithography,” Appl. Opt.48(24), 4801–4813 (2009).
[CrossRef] [PubMed]

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

2008 (4)

C. Webb, “45nm design for manufacturing,” Intel Technol. J.12, 121–130 (2008).

M. C. Smayling, H.- Liu, and L. Cai, “Low k1 logic design using gridded design rules,” Proc. SPIE6925, 69250B, 69250B-7 (2008).
[CrossRef]

J. L. Stay and T. K. Gaylord, “Three-beam-interference lithography: contrast and crystallography,” Appl. Opt.47(18), 3221–3230 (2008).
[CrossRef] [PubMed]

M. C. Smayling, C. Bencher, H. D. Chen, H. Dai, and M. P. Duane, “APF pitch-halving for 22 nm logic cells using gridded design rules,” Proc. SPIE6925, 69251E, 69251E-8 (2008).
[CrossRef]

2007 (1)

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

2005 (2)

J. Wang, A. K. Wong, and E. Y. Lam, “Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates,” J. Microlithogr., Microfabr., Microsyst.4, 013001 (2005).

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

2004 (4)

M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, “Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm,” Proc. SPIE5754, 1508–1518 (2004).
[CrossRef]

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

B. J. Lin, “Simulation of optical projection with polarization-dependent stray light to explore the difference between dry and immersion lithography,” J. Microlithogr., Microfabr., Microsyst.3, 9–20 (2004).

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

2003 (5)

M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins, and P. M. Martin, “Dense only phase shift template lithography,” Proc. SPIE5042, 15–29 (2003).
[CrossRef]

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

C. A. Mack, “Off-axis illumination,” Microlithogr. World12, 14–16 (2003).

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

2002 (1)

M. Switkes and M. Rothschild, “Resolution enhancement of 157 nm lithography by liquid immersion,” Proc. SPIE4691, 459–465 (2002).
[CrossRef]

2001 (2)

A. Yen, S. S. Yu, J. H. Chen, C. K. Chen, T. S. Gau, and B. J. Lin, “Low-k1 optical lithography for 100 nm logic technology and beyond,” J. Vac. Sci. Technol. B19(6), 2329–2334 (2001).
[CrossRef]

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

1999 (2)

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

A. Suzuki, K. Saitoh, and M. Yoshii, “Multilevel imaging system realizing k1=0.3 lithography,” Proc. SPIE3679, 396–407 (1999).
[CrossRef]

1996 (1)

N. Cobb, A. Zakhor, and E. Miloslavsky, “Mathematical and CAD framework for proximity correction,” Proc. SPIE2726, 208–222 (1996).
[CrossRef]

1995 (1)

M. S. Hibbs and R. R. Kunz, “193-nm full-field step-and-scan prototype at MIT Lincoln Lab,” Proc. SPIE2440, 40–48 (1995).
[CrossRef]

1993 (1)

K. Kamon, T. Miyamoto, Y. Myoi, H. Nagata, and M. Tanaka, “Photolithography system using modified illumination,” Jpn. J. Appl. Phys.32(Part 1), 239–243 (1993).
[CrossRef]

1992 (2)

1982 (1)

M. D. Levenson, N. S. Viswanathan, and R. A. Simpson, “Improving resolution in photolithography with a phase-shifting mask,” IEEE Trans. Electron. Dev.29(12), 1828–1836 (1982).
[CrossRef]

Barish, A.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

Baum, Z.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

Bencher, C.

M. C. Smayling, C. Bencher, H. D. Chen, H. Dai, and M. P. Duane, “APF pitch-halving for 22 nm logic cells using gridded design rules,” Proc. SPIE6925, 69251E, 69251E-8 (2008).
[CrossRef]

Bloomstein, T. M.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Bonges, H.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

Bourov, A.

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

Brooker, P.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

Bukofsky, S.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

Burrow, G. M.

G. M. Burrow, M. C. R. Leibovici, J. W. Kummer, and T. K. Gaylord, “Pattern-integrated interference lithography instrumentation,” Rev. Sci. Instrum.83(6), 063707 (2012).
[CrossRef] [PubMed]

G. M. Burrow, M. C. R. Leibovici, and T. K. Gaylord, “Pattern-integrated interference lithography: single-exposure fabrication of photonic-crystal structures,” Appl. Opt.51(18), 4028–4041 (2012).
[CrossRef] [PubMed]

J. L. Stay, G. M. Burrow, and T. K. Gaylord, “Three-beam interference lithography methodology,” Rev. Sci. Instrum.82(2), 023115 (2011).
[CrossRef] [PubMed]

Cai, L.

M. C. Smayling, H.- Liu, and L. Cai, “Low k1 logic design using gridded design rules,” Proc. SPIE6925, 69250B, 69250B-7 (2008).
[CrossRef]

Cann, S.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

Cerrina, F.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Chen, C. K.

A. Yen, S. S. Yu, J. H. Chen, C. K. Chen, T. S. Gau, and B. J. Lin, “Low-k1 optical lithography for 100 nm logic technology and beyond,” J. Vac. Sci. Technol. B19(6), 2329–2334 (2001).
[CrossRef]

Chen, H. D.

M. C. Smayling, C. Bencher, H. D. Chen, H. Dai, and M. P. Duane, “APF pitch-halving for 22 nm logic cells using gridded design rules,” Proc. SPIE6925, 69251E, 69251E-8 (2008).
[CrossRef]

Chen, J. H.

A. Yen, S. S. Yu, J. H. Chen, C. K. Chen, T. S. Gau, and B. J. Lin, “Low-k1 optical lithography for 100 nm logic technology and beyond,” J. Vac. Sci. Technol. B19(6), 2329–2334 (2001).
[CrossRef]

Cobb, N.

N. Cobb, A. Zakhor, and E. Miloslavsky, “Mathematical and CAD framework for proximity correction,” Proc. SPIE2726, 208–222 (1996).
[CrossRef]

Cropanese, F.

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

Culp, J.

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

Dai, H.

M. C. Smayling, C. Bencher, H. D. Chen, H. Dai, and M. P. Duane, “APF pitch-halving for 22 nm logic cells using gridded design rules,” Proc. SPIE6925, 69251E, 69251E-8 (2008).
[CrossRef]

David, C.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Duane, M. P.

M. C. Smayling, C. Bencher, H. D. Chen, H. Dai, and M. P. Duane, “APF pitch-halving for 22 nm logic cells using gridded design rules,” Proc. SPIE6925, 69251E, 69251E-8 (2008).
[CrossRef]

Efremow, N. N.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Fan, Y. F.

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

Fedynyshyn, T. H.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Fonseca, C.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

Fritze, M.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins, and P. M. Martin, “Dense only phase shift template lithography,” Proc. SPIE5042, 15–29 (2003).
[CrossRef]

Gau, T. S.

A. Yen, S. S. Yu, J. H. Chen, C. K. Chen, T. S. Gau, and B. J. Lin, “Low-k1 optical lithography for 100 nm logic technology and beyond,” J. Vac. Sci. Technol. B19(6), 2329–2334 (2001).
[CrossRef]

Gaylord, T. K.

Gobrecht, J.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Golovkina, V.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Graur, I.

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

Greenway, R. T.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

Grenville, A.

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Halle, S.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

Hardy, D. E.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Hendel, R.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

Hersan, T.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Hibbs, M.

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

Hibbs, M. S.

M. S. Hibbs and R. R. Kunz, “193-nm full-field step-and-scan prototype at MIT Lincoln Lab,” Proc. SPIE2440, 40–48 (1995).
[CrossRef]

Jeong, K.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

Jhaveri, T.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Kahng, A. B.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

Kamon, K.

K. Kamon, T. Miyamoto, Y. Myoi, H. Nagata, and M. Tanaka, “Photolithography system using modified illumination,” Jpn. J. Appl. Phys.32(Part 1), 239–243 (1993).
[CrossRef]

Kang, H. Y.

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

Kheterpal, V.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Kim, S. O.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Kim Yaw, T.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Kummer, J. W.

G. M. Burrow, M. C. R. Leibovici, J. W. Kummer, and T. K. Gaylord, “Pattern-integrated interference lithography instrumentation,” Rev. Sci. Instrum.83(6), 063707 (2012).
[CrossRef] [PubMed]

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M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

M. S. Hibbs and R. R. Kunz, “193-nm full-field step-and-scan prototype at MIT Lincoln Lab,” Proc. SPIE2440, 40–48 (1995).
[CrossRef]

Lafferty, N.

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

Lai, K. F.

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

Lam, E. Y.

J. Wang, A. K. Wong, and E. Y. Lam, “Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates,” J. Microlithogr., Microfabr., Microsyst.4, 013001 (2005).

Leibovici, M. C. R.

G. M. Burrow, M. C. R. Leibovici, J. W. Kummer, and T. K. Gaylord, “Pattern-integrated interference lithography instrumentation,” Rev. Sci. Instrum.83(6), 063707 (2012).
[CrossRef] [PubMed]

G. M. Burrow, M. C. R. Leibovici, and T. K. Gaylord, “Pattern-integrated interference lithography: single-exposure fabrication of photonic-crystal structures,” Appl. Opt.51(18), 4028–4041 (2012).
[CrossRef] [PubMed]

Leipold, W.

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

Lennon, D.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

Levenson, M. D.

M. D. Levenson, N. S. Viswanathan, and R. A. Simpson, “Improving resolution in photolithography with a phase-shifting mask,” IEEE Trans. Electron. Dev.29(12), 1828–1836 (1982).
[CrossRef]

Liberman, V.

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Liebmann, L.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

Lin, B. J.

B. J. Lin, “Simulation of optical projection with polarization-dependent stray light to explore the difference between dry and immersion lithography,” J. Microlithogr., Microfabr., Microsyst.3, 9–20 (2004).

A. Yen, S. S. Yu, J. H. Chen, C. K. Chen, T. S. Gau, and B. J. Lin, “Low-k1 optical lithography for 100 nm logic technology and beyond,” J. Vac. Sci. Technol. B19(6), 2329–2334 (2001).
[CrossRef]

B. J. Lin, “The attenuated phase-shifting mask,” Solid State Technol.35, 43–47 (1992).

Liu, H.-

M. C. Smayling, H.- Liu, and L. Cai, “Low k1 logic design using gridded design rules,” Proc. SPIE6925, 69250B, 69250B-7 (2008).
[CrossRef]

Mack, C. A.

C. A. Mack, “Off-axis illumination,” Microlithogr. World12, 14–16 (2003).

Maenhoudt, M.

M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, “Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm,” Proc. SPIE5754, 1508–1518 (2004).
[CrossRef]

Mallen, R. D.

M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins, and P. M. Martin, “Dense only phase shift template lithography,” Proc. SPIE5042, 15–29 (2003).
[CrossRef]

Martin, P. M.

M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins, and P. M. Martin, “Dense only phase shift template lithography,” Proc. SPIE5042, 15–29 (2003).
[CrossRef]

Miloslavsky, E.

N. Cobb, A. Zakhor, and E. Miloslavsky, “Mathematical and CAD framework for proximity correction,” Proc. SPIE2726, 208–222 (1996).
[CrossRef]

Miyamoto, T.

K. Kamon, T. Miyamoto, Y. Myoi, H. Nagata, and M. Tanaka, “Photolithography system using modified illumination,” Jpn. J. Appl. Phys.32(Part 1), 239–243 (1993).
[CrossRef]

Molless, A.

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

Motiani, D.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Myoi, Y.

K. Kamon, T. Miyamoto, Y. Myoi, H. Nagata, and M. Tanaka, “Photolithography system using modified illumination,” Jpn. J. Appl. Phys.32(Part 1), 239–243 (1993).
[CrossRef]

Nagata, H.

K. Kamon, T. Miyamoto, Y. Myoi, H. Nagata, and M. Tanaka, “Photolithography system using modified illumination,” Jpn. J. Appl. Phys.32(Part 1), 239–243 (1993).
[CrossRef]

Nealey, P. F.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Northrop, G.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

Oberschmidt, J.

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

O'Grady, D.

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

Palmacci, S. T.

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Pandini, D.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Petersen, J. S.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

Pileggi, L.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Rao, Z.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

Regaill, D.

L. Liebmann, I. Graur, W. Leipold, J. Oberschmidt, D. O'Grady, and D. Regaill, “Alternating phase shifted mask for logic gate levels, design and mask manufacturing,” Proc. SPIE3679, 27–37 (1999).
[CrossRef]

Rhyins, P. D.

M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins, and P. M. Martin, “Dense only phase shift template lithography,” Proc. SPIE5042, 15–29 (2003).
[CrossRef]

Rosenbluth, A. E.

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

Rothschild, M.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

M. Switkes and M. Rothschild, “Resolution enhancement of 157 nm lithography by liquid immersion,” Proc. SPIE4691, 459–465 (2002).
[CrossRef]

Rovner, V.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Runyon, S.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

Saitoh, K.

A. Suzuki, K. Saitoh, and M. Yoshii, “Multilevel imaging system realizing k1=0.3 lithography,” Proc. SPIE3679, 396–407 (1999).
[CrossRef]

Schattenburg, M. L.

Sedlacek, J. H. C.

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

Sigal, L.

L. Liebmann, A. Barish, Z. Baum, H. Bonges, S. Bukofsky, C. Fonseca, S. Halle, G. Northrop, S. Runyon, and L. Sigal, “High-performance circuit design for the RET-enabled 65nm technology node,” Proc. SPIE5379, 20–29 (2004).
[CrossRef]

L. Liebmann, G. Northrop, J. Culp, L. Sigal, A. Barish, and C. Fonseca, “Layout optimization at the pinnacle of optical lithography,” Proc. SPIE5042, 1–14 (2003).
[CrossRef]

Simpson, R. A.

M. D. Levenson, N. S. Viswanathan, and R. A. Simpson, “Improving resolution in photolithography with a phase-shifting mask,” IEEE Trans. Electron. Dev.29(12), 1828–1836 (1982).
[CrossRef]

Singh, R. N.

A. E. Rosenbluth, S. Bukofsky, M. Hibbs, K. F. Lai, A. Molless, R. N. Singh, and A. Wong, “Optimum mask and source patterns to print a given shape,” Proc. SPIE4346, 486–502 (2001).
[CrossRef]

Smayling, M. C.

R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao, and M. C. Smayling, “Interference assisted lithography for patterning of 1D gridded design,” Proc. SPIE7271, 72712U, 72712U-11 (2009).
[CrossRef]

M. C. Smayling, H.- Liu, and L. Cai, “Low k1 logic design using gridded design rules,” Proc. SPIE6925, 69250B, 69250B-7 (2008).
[CrossRef]

M. C. Smayling, C. Bencher, H. D. Chen, H. Dai, and M. P. Duane, “APF pitch-halving for 22 nm logic cells using gridded design rules,” Proc. SPIE6925, 69251E, 69251E-8 (2008).
[CrossRef]

Smith, B. W.

B. W. Smith, A. Bourov, H. Y. Kang, F. Cropanese, Y. F. Fan, N. Lafferty, and L. Zavyalova, “Water immersion optical lithography at 193 nm,” J. Microlithogr., Microfabr., Microsyst.3, 44–51 (2004).

Smith, H. I.

Solak, H. H.

H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. O. Kim, and P. F. Nealey, “Sub-50 nm period patterns with EUV interference lithography,” Microelectron. Eng.67–68, 56–62 (2003).
[CrossRef]

Spector, S.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

Stay, J. L.

Strojwas, A. J.

T. Jhaveri, V. Rovner, L. Pileggi, A. J. Strojwas, D. Motiani, V. Kheterpal, T. Kim Yaw, T. Hersan, and D. Pandini, “Maximization of layout printability/manufacturability by extreme layout regularity,” J. Microlithogr., Microfabr., Microsyst.6, 031011 (2007).

Struyf, H.

M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, “Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm,” Proc. SPIE5754, 1508–1518 (2004).
[CrossRef]

Suzuki, A.

A. Suzuki, K. Saitoh, and M. Yoshii, “Multilevel imaging system realizing k1=0.3 lithography,” Proc. SPIE3679, 396–407 (1999).
[CrossRef]

Switkes, M.

M. Rothschild, T. M. Bloomstein, T. H. Fedynyshyn, R. R. Kunz, V. Liberman, M. Switkes, N. N. Efremow, S. T. Palmacci, J. H. C. Sedlacek, D. E. Hardy, and A. Grenville, “Recent trends in optical lithography,” Lincoln Lab. J.14, 221–236 (2003).

M. Switkes and M. Rothschild, “Resolution enhancement of 157 nm lithography by liquid immersion,” Proc. SPIE4691, 459–465 (2002).
[CrossRef]

Tanaka, M.

K. Kamon, T. Miyamoto, Y. Myoi, H. Nagata, and M. Tanaka, “Photolithography system using modified illumination,” Jpn. J. Appl. Phys.32(Part 1), 239–243 (1993).
[CrossRef]

Tyrrell, B.

M. Fritze, T. M. Bloomstein, B. Tyrrell, T. H. Fedynyshyn, N. N. Efremow, D. E. Hardy, S. Cann, D. Lennon, S. Spector, M. Rothschild, and P. Brooker, “Hybrid optical maskless lithography: scaling beyond the 45 nm node,” J. Vac. Sci. Technol. B23(6), 2743–2748 (2005).
[CrossRef]

M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins, and P. M. Martin, “Dense only phase shift template lithography,” Proc. SPIE5042, 15–29 (2003).
[CrossRef]

Van Hove, M.

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Appl. Opt. (4)

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Proc. SPIE (13)

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Figures (5)

Fig. 1
Fig. 1

Three-beam PIIES. This PIIES illumination system provides a coherent illumination of the blocking pattern mask located at the pattern mask plane. The PIIES compound objective lens images the blocking elements at the wafer plane. Simultaneously, the PIIES compound objective lens collimates the beams at the wafer plane, thereby integrating the blocking elements of the mask in a three-beam interference pattern in a single-exposure step.

Fig. 2
Fig. 2

PIIES single-exposure fabrication result. (a) 600.0 μm x 600.0 μm Greek-cross blocking element; (b) SEM image of the single-exposure integration of the reduced Greek cross within a three-beam interference pattern; (c) Magnified SEM view of the top-right corner of the Greek cross integrated within a 2D square-lattice periodic pattern with a lattice constant a=1.0μm .

Fig. 3
Fig. 3

PIIES single-exposure fabrication result. (a) 20.0 μm x 2.0 μm line segment blocking element; (b) SEM image of the single-exposure integration of the reduced line segment within a three-beam interference pattern; (c) Magnified SEM view of the line segment integrated within a 2D square-lattice periodic pattern with a lattice constant a=1.0μm .

Fig. 4
Fig. 4

Distribution of attenuating elements in the Fourier plane that is needed to reduce further light in the modified interference pattern in the wafer plane associated with blocking elements in the pattern mask plane. The quantities fx and fy represent the spatial frequencies in the x and y directions respectively in the pattern mask plane. Due to the periodic repetition of bitcells in the SRAM design, the attenuating elements occur at corresponding fundamental and harmonic spatial frequencies in the Fourier plane as shown in this figure.

Fig. 5
Fig. 5

Example implementation of PIIL through DPM. (a) A reference beam is added to the PIIES using a lens and a pellicle to record interferometrically the integrated-pattern-mask information at the DPM surface. (b) Once developed and properly illuminated, the DPM duplicates the PIIES interfering beams, which, in turn, form the designed pattern-integrated optical-intensity distribution.

Tables (1)

Tables Icon

Table 1 Single-step combinations of 1D and 2D interference patterns with integrated blocking elements to produce SRAM bitcell exposures as implemented by PIIL. A single bitcell is indicated by the dashed line.

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