Abstract

We propose a most economical design of the Optical Shared MemOry Supercomputer Interconnect System (OSMOSIS) all-optical, wavelength-space crossbar switch fabric. It is shown, by analysis and simulation, that the total number of on-off gates required for the proposed N × N switch fabric can scale asymptotically as N ln N if the number of input/output ports N can be factored into a product of small primes. This is of the same order of magnitude as Shannon’s lower bound for switch complexity, according to which the minimum number of two-state switches required for the construction of a N × N permutation switch is log2 (N!).

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References

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  1. The Top 500 Supercomputer Sites, http://www.top500.org .
  2. R. Hemenway, R. R. Grzybowski, C. Minkenberg, and R. Luijten, “Optical-packet-switched interconnect for supercomputer applications,” J. Opt. Netw. 3(12), 900–913 (2004).
    [CrossRef]
  3. R. Luijten, W. E. Denzel, R. R. Grzybowski, and R. Hemenway, “Optical interconnection networks: The OSMOSIS project,” in Proceedings of IEEE Lasers and Electro-Optics Society 17th Annual Meeting, Rio Grande, Puerto Rico, (2004), 563–564.
  4. R. Luijten, C. Minkenberg, R. Hemenway, M. Sauer, and R. Grzybowski, “Viable opto-electronic HPC interconnect fabrics,” in Proceedings of ACM/IEEE SC2005 Conference on High Performance Networking and Computing, Seattle, WA, USA, (2005).
  5. R. Luijten, C. Minkenberg, B. R. Hemenway, and R. R. Grzybowski, “Implementation challenges in the OSMOSIS optical HPC switch,” in Proceedings of IEEE Lasers and Electro-Optics Society 19th Annual Meeting, Montreal, CA, (2006), 623–624.
  6. M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
    [CrossRef]
  7. I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Optimization of a supercomputer optical interconnect architecture,” in Proceedings of IEEE Lasers and Electro-Optics Society 20th Annual Meeting, Orlando, FL, (2007), 741–742.
  8. R. P. Luijten and R. Grzybowski, “The OSMOSIS Optical Packet Switch for Supercomputers,” in Proceedings of IEEE/OSA Optical Fiber Communication Conference, San Diego, CA, (2009), pp. 1–3.
  9. W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C: the Art of Scientific Computing, 2nd ed. (Cambridge University Press, 1992).
  10. M. Zirngibl, C. H. Joyner, and B. Glance, “Digitally tunable channel dropping filter/equalizer based on waveguide grating router and optical amplifier integration,” IEEE Photon. Technol. Lett. 6(4), 513–515 (1994).
    [CrossRef]
  11. L. Kleinrock and F. Kamoun, “Hierarchical routing for large networks–performance evaluation and optimization,” Comput. Netw. 1, 82–92 (1977).
  12. O. Ishida, H. Takahashi, and Y. Inoue, “Digitally tunable optical filters using arrayed-waveguide grating (AWG) multiplexers and optical switches,” J. Lightwave Technol. 15(2), 321–327 (1997).
    [CrossRef]
  13. A. Misawa, K. Sasayama, and Y. Yamada, “WDM knockout switch with multi-output-port wavelength channel selectors,” J. Lightwave Technol. 16(12), 2212–2219 (1998).
    [CrossRef]
  14. N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
    [CrossRef]
  15. N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
    [CrossRef]
  16. N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
    [CrossRef]
  17. G. Arfken, Mathematical Methods for Physicists, 3d ed. (Academic Press, 1985).
  18. G. L. Nemhauser and L. A. Wolsey, Integer and Combinatorial Optimization (Wiley, 1999).
  19. M. A. Saad, Thermodynamics: Principles and Practice (Prentice Hall, 1997).
  20. P. E. Green, Fiber-Optic Networks (Prentice Hall, 1993).
  21. F. Karinou, I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Physical layer performance of HPC optical interconnect architectures,” J. Lightwave Technol.29(21), 3167–3177 (2011).

2006 (1)

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

2004 (2)

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

R. Hemenway, R. R. Grzybowski, C. Minkenberg, and R. Luijten, “Optical-packet-switched interconnect for supercomputer applications,” J. Opt. Netw. 3(12), 900–913 (2004).
[CrossRef]

2003 (1)

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

2002 (1)

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

1998 (1)

1997 (1)

O. Ishida, H. Takahashi, and Y. Inoue, “Digitally tunable optical filters using arrayed-waveguide grating (AWG) multiplexers and optical switches,” J. Lightwave Technol. 15(2), 321–327 (1997).
[CrossRef]

1994 (1)

M. Zirngibl, C. H. Joyner, and B. Glance, “Digitally tunable channel dropping filter/equalizer based on waveguide grating router and optical amplifier integration,” IEEE Photon. Technol. Lett. 6(4), 513–515 (1994).
[CrossRef]

1977 (1)

L. Kleinrock and F. Kamoun, “Hierarchical routing for large networks–performance evaluation and optimization,” Comput. Netw. 1, 82–92 (1977).

Dickens, J.

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

Glance, B.

M. Zirngibl, C. H. Joyner, and B. Glance, “Digitally tunable channel dropping filter/equalizer based on waveguide grating router and optical amplifier integration,” IEEE Photon. Technol. Lett. 6(4), 513–515 (1994).
[CrossRef]

Grzybowski, R.

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

Grzybowski, R. R.

R. Hemenway, R. R. Grzybowski, C. Minkenberg, and R. Luijten, “Optical-packet-switched interconnect for supercomputer applications,” J. Opt. Netw. 3(12), 900–913 (2004).
[CrossRef]

F. Karinou, I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Physical layer performance of HPC optical interconnect architectures,” J. Lightwave Technol.29(21), 3167–3177 (2011).

Hemenway, B. R.

F. Karinou, I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Physical layer performance of HPC optical interconnect architectures,” J. Lightwave Technol.29(21), 3167–3177 (2011).

Hemenway, R.

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

R. Hemenway, R. R. Grzybowski, C. Minkenberg, and R. Luijten, “Optical-packet-switched interconnect for supercomputer applications,” J. Opt. Netw. 3(12), 900–913 (2004).
[CrossRef]

Inoue, Y.

O. Ishida, H. Takahashi, and Y. Inoue, “Digitally tunable optical filters using arrayed-waveguide grating (AWG) multiplexers and optical switches,” J. Lightwave Technol. 15(2), 321–327 (1997).
[CrossRef]

Ishida, O.

O. Ishida, H. Takahashi, and Y. Inoue, “Digitally tunable optical filters using arrayed-waveguide grating (AWG) multiplexers and optical switches,” J. Lightwave Technol. 15(2), 321–327 (1997).
[CrossRef]

Ishii, H.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Joyner, C. H.

M. Zirngibl, C. H. Joyner, and B. Glance, “Digitally tunable channel dropping filter/equalizer based on waveguide grating router and optical amplifier integration,” IEEE Photon. Technol. Lett. 6(4), 513–515 (1994).
[CrossRef]

Kamoun, F.

L. Kleinrock and F. Kamoun, “Hierarchical routing for large networks–performance evaluation and optimization,” Comput. Netw. 1, 82–92 (1977).

Karfelt, R.

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

Karinou, F.

F. Karinou, I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Physical layer performance of HPC optical interconnect architectures,” J. Lightwave Technol.29(21), 3167–3177 (2011).

Kawaguchi, Y.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Kikuchi, N.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Kleinrock, L.

L. Kleinrock and F. Kamoun, “Hierarchical routing for large networks–performance evaluation and optimization,” Comput. Netw. 1, 82–92 (1977).

Kondo, Y.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

Luijten, R.

Minkenberg, C.

Misawa, A.

Okamoto, H.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Oku, S.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Peters, D.

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

Roudas, I.

F. Karinou, I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Physical layer performance of HPC optical interconnect architectures,” J. Lightwave Technol.29(21), 3167–3177 (2011).

Sasayama, K.

Sauer, M.

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

Shibata, Y.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Takahashi, H.

O. Ishida, H. Takahashi, and Y. Inoue, “Digitally tunable optical filters using arrayed-waveguide grating (AWG) multiplexers and optical switches,” J. Lightwave Technol. 15(2), 321–327 (1997).
[CrossRef]

Tohmori, Y.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Yamada, Y.

Yoshikuni, Y.

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

Zirngibl, M.

M. Zirngibl, C. H. Joyner, and B. Glance, “Digitally tunable channel dropping filter/equalizer based on waveguide grating router and optical amplifier integration,” IEEE Photon. Technol. Lett. 6(4), 513–515 (1994).
[CrossRef]

Comput. Netw. (1)

L. Kleinrock and F. Kamoun, “Hierarchical routing for large networks–performance evaluation and optimization,” Comput. Netw. 1, 82–92 (1977).

Electron. Lett. (2)

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM channel selector with novel configuration,” Electron. Lett. 38(7), 331–332 (2002).
[CrossRef]

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, H. Ishii, Y. Yoshikuni, and Y. Tohmori, “Monolithically integrated 64-channel WDM wavelength selective receiver,” Electron. Lett. 39(3), 312–314 (2003).
[CrossRef]

IEEE Photon. Technol. Lett. (2)

N. Kikuchi, Y. Shibata, H. Okamoto, Y. Kawaguchi, S. Oku, Y. Kondo, and Y. Tohmori, “Monolithically integrated 100-channel WDM channel selector employing low-crosstalk AWG,” IEEE Photon. Technol. Lett. 16(11), 2481–2483 (2004).
[CrossRef]

M. Zirngibl, C. H. Joyner, and B. Glance, “Digitally tunable channel dropping filter/equalizer based on waveguide grating router and optical amplifier integration,” IEEE Photon. Technol. Lett. 6(4), 513–515 (1994).
[CrossRef]

J. Lightwave Technol. (2)

A. Misawa, K. Sasayama, and Y. Yamada, “WDM knockout switch with multi-output-port wavelength channel selectors,” J. Lightwave Technol. 16(12), 2212–2219 (1998).
[CrossRef]

O. Ishida, H. Takahashi, and Y. Inoue, “Digitally tunable optical filters using arrayed-waveguide grating (AWG) multiplexers and optical switches,” J. Lightwave Technol. 15(2), 321–327 (1997).
[CrossRef]

J. Opt. Netw. (1)

Proc. SPIE (1)

M. Sauer, R. Hemenway, R. Grzybowski, D. Peters, J. Dickens, and R. Karfelt, “A scaleable optical interconnect for low-latency cell switching in high-performance computing systems,” Proc. SPIE 6124, 61240N, 61240N-12 (2006).
[CrossRef]

Other (12)

I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Optimization of a supercomputer optical interconnect architecture,” in Proceedings of IEEE Lasers and Electro-Optics Society 20th Annual Meeting, Orlando, FL, (2007), 741–742.

R. P. Luijten and R. Grzybowski, “The OSMOSIS Optical Packet Switch for Supercomputers,” in Proceedings of IEEE/OSA Optical Fiber Communication Conference, San Diego, CA, (2009), pp. 1–3.

W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C: the Art of Scientific Computing, 2nd ed. (Cambridge University Press, 1992).

R. Luijten, W. E. Denzel, R. R. Grzybowski, and R. Hemenway, “Optical interconnection networks: The OSMOSIS project,” in Proceedings of IEEE Lasers and Electro-Optics Society 17th Annual Meeting, Rio Grande, Puerto Rico, (2004), 563–564.

R. Luijten, C. Minkenberg, R. Hemenway, M. Sauer, and R. Grzybowski, “Viable opto-electronic HPC interconnect fabrics,” in Proceedings of ACM/IEEE SC2005 Conference on High Performance Networking and Computing, Seattle, WA, USA, (2005).

R. Luijten, C. Minkenberg, B. R. Hemenway, and R. R. Grzybowski, “Implementation challenges in the OSMOSIS optical HPC switch,” in Proceedings of IEEE Lasers and Electro-Optics Society 19th Annual Meeting, Montreal, CA, (2006), 623–624.

G. Arfken, Mathematical Methods for Physicists, 3d ed. (Academic Press, 1985).

G. L. Nemhauser and L. A. Wolsey, Integer and Combinatorial Optimization (Wiley, 1999).

M. A. Saad, Thermodynamics: Principles and Practice (Prentice Hall, 1997).

P. E. Green, Fiber-Optic Networks (Prentice Hall, 1993).

F. Karinou, I. Roudas, B. R. Hemenway, and R. R. Grzybowski, “Physical layer performance of HPC optical interconnect architectures,” J. Lightwave Technol.29(21), 3167–3177 (2011).

The Top 500 Supercomputer Sites, http://www.top500.org .

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Figures (17)

Fig. 1
Fig. 1

(a) Broadcast-and-select architecture using a star coupler, N fixed transmitters and N tunable receivers. (b) Actual implementation. (Symbols: Tx = Transmitter, Rx = Receiver, SOA = Semiconductor optical amplifier, MUX = Multiplexer, DMUX = Demultiplexer).

Fig. 2
Fig. 2

(a) Schematic diagram illustrating the operation of a single-stage 16-channel selector using an arrayed waveguide grating (AWG) demultiplexer/multiplexer (MUX/DMUX) pair and 16 semiconductor optical amplifiers. (b) Visualization of the functionality in the frequency domain.

Fig. 3
Fig. 3

(a) Schematic diagram illustrating the operation of a two-stage 16-channel selector, which is functionally equivalent to the single-stage 16-channel selector shown in Fig. 2(a). The two-stage selector uses two arrayed waveguide grating (AWG) demultiplexer/multiplexer (MUX/DMUX) pairs and 8 semiconductor optical amplifiers. (b) Visualization of the functionality in the frequency domain.

Fig. 4
Fig. 4

Multiplexing/demultiplexing functionalities of the 16 × 16 optical interconnect of Fig. 3. (a) At the transmitter, the 16-channel multiplexing hierarchy can be represented by a tree structure. The root tributary is composed of four wavebands of four wavelengths each. (Symbols: The four wavebands are denoted from left to right with black, red, green, and blue lines. Same color code is used for the wavelengths within each waveband). (b) At the receiver, it is possible to reduce the number of SOAs by folding the tree structure of the multiplexing hierarchy, exploiting the periodicity of the AWG transfer function. The folded tree, as it appears after a Waveband MUX/DMUX pair and an AWG Wavelength DMUX, is shown here. By placing SOAs at the arms of the DMUXs at the waveband- and wavelength-level (i.e., the branches and the leaves of the folded tree), it is possible to reduce the number of SOAs by half. In order to achieve this, the wavelength DMUX must be an AWG.

Fig. 5
Fig. 5

Alternative implementation of the multiplexing/demultiplexing functionalities of Fig. 4. (a) At the transmitter, hierarchical multiplexing is performed using four fibers carrying the same set of four wavelengths, instead of one fiber carrying four wavebands of four distinct wavelengths each (i.e., a total of 16 wavelengths) as in Fig. 4; (b) Receiver: The Waveband MUX/DMUX pair at the receiver of Fig. 4 is omitted here. The Waveband MUX at the receiver of Fig. 4 is substituted by a combiner. The folded tree, as it appears after a combiner and a Wavelength DMUX, is shown here. By placing SOAs at the arms of the DMUXs at the fiber- and wavelength-level (i.e., the branches and the leaves of the folded tree), it is possible to reduce the number of SOAs by half. The wavelength DMUX does not have to be AWG.

Fig. 6
Fig. 6

All possible 16-wavelength multiplexing hierarchies and their corresponding discretely-tunable, multi-stage, channel selector layouts.

Fig. 7
Fig. 7

(a) Example of K multiplexing stages with n1 channels per waveband of order one (i = 1), n2 wavebands of order one per waveband of order two (i = 2), and so on. The K-th multiplexing stage can be implemented using spatial division multiplexing (SDM) of nk optical fibers, in order to allow wavelength reuse and hence, reduce the total number of wavelengths required. In this case, the K-th multiplexer should be omitted. The rest of the multiplexers (denoted by broken trapezoids) are optional, if a N × N star coupler is used instead of a splitter, as in Fig. 1(b). However, in practice, multiplexers might be required, in order to reduce adjacent channel crosstalk. (b) Layout of a receiver card with K channel selection stages. The numbering of the selection stages is done in reverse order from left to right. The MUX/DMUX pair corresponding to the K-th order channel selector (denoted by broken trapezoids) might be omitted if the K-th multiplexing stage at the transmitter is implemented using spatial division multiplexing (SDM) of nk optical fibers.

Fig. 8
Fig. 8

Graphical solution of the constrained optimization problem regarding the optimal two-stage multiplexing hierarchy for 16 channels. (Symbols: Green line: cost function Eq. (2), Red line: constraint Eq. (1), Points: feasible integer solutions. Shades of gray: contours of the cost function. Shading becomes darker as we move to smaller values).

Fig. 9
Fig. 9

Number of SOAs required per receiver card for 64 channels partitioned in tributaries of K selection stages. Solid line: expression (11), Points: last column of Table 1.

Fig. 10
Fig. 10

(a) Implementation of the optimal, 64-channel, 3-level multiplexing hierarchy for the proposed optical crossbar switch fabric, and (b) Implementation of an optimal, 64-channel, discretely-tunable direct-detection receiver, for the multiplexing hierarchy shown in Fig. 10(a).

Fig. 11
Fig. 11

Number of SOAs required per receiver card for (a) 256, (b) 72, and (c) 96 channels partitioned in tributaries of Κselection stages. Solid line: Eq. (11). (d) Comparison of the optimality of the best channel selectors for 64, 72, 96 and 256 channels, as a function of the number of selection stages

Fig. 12
Fig. 12

(a) Optimality factor and (b) Gain in the number of SOAs as a function of the number of channels, using a multi-stage channel selector.

Fig. 13
Fig. 13

The rule used for setting the on-off SOA gates of the K channel selection stages of the m-th receiver.

Fig. 14
Fig. 14

(a) Example of transmitter/receiver numbering in a 64 × 64 broadcast and select architecture. In parentheses, channel indices are expressed in base-4. In this example, the transmitter with index #37 [(211)4in base-4] is connected to the receiver with index #16. (b) Layout of the 16-th receiver card with 3 channel selection stages. The SOA numbering of each selection stage is shown. The three digits of the base-4 transmitter index are used to set the shaded (red) SOAs ON at the three selection stages.

Fig. 15
Fig. 15

The SOA setting shown in Fig. 14(b) selects the channel with index #37 out of the 64 wavelength tree, by first selecting the third fiber, then, the second waveband of this fiber, and finally, the second channel in this waveband (thick solid line).

Fig. 16
Fig. 16

Normalized cost function (per unit SOA cost) for N = 64 and r = 0 – 2 using direct enumeration. (Symbols: expression (25) and best realizations of Table 1).

Fig. 17
Fig. 17

Normalized cost function (per unit SOA cost) for N = 256 and r = 0 – 2 using direct enumeration.

Tables (1)

Tables Icon

Table 1 Unrestricted additive partitions of 64 channels in tributaries of K channel selection stages and number of SOAs required per receiver card for each realization.

Equations (33)

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N= i=1 K n i
Ω= i=1 K n i
Ω tot =NΩ
δΩ= i=1 K δ n i =0
i=1 K ( δ n i j=1 ji K n j ) =0
i=1 K δ n i n i =0
i=1 K δ n i λ i=1 K δ n i n i =0
i=1 K δ n i ( 1 λ n i )=0
n i =λ
N = (1) i=1 K n i = (9) λ K λ= N K
Ω min|K = (2),(10) K N K
Ω tot|K min = (3),(11) NK N K
K opt =lnN
Ω min = (11),(13) lnNe
Ω tot min = (12),(13) NlnNe
F= Ω min Ω
G= N Ω
N= 2 N'
n i = 2 n i '
N'= i=1 K n i '
mK=N'
n 1 = n 2 == n 6 =2 (m=1) n 1 = n 2 = n 3 =4 (m=2) n 1 = n 2 =8 (m=3)
N= i=1 M p i m i
K= i=1 M m i
Ω= i=1 M m i p i
υ i =( 0 1 0 ) i=K,,1
Ω= 2KA MUX/DMUX cost + B i=1 K n i SOA cost
Ω min|K = (10),(25) 2KA+BK N K
K opt = 1 x lnN
x1=r e x
Ω min = (26),(27) ylnN
Ω tot min = (3),(29) yNlnN
y=B r+ e x x

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