Abstract

This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process. By utilizing existing front-end fabrication processes the photonic devices are monolithically integrated with electronics in the same physical device layer as transistors achieving 4 ps logic stage delay, without degradation in transistor performance. We demonstrate an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits. By developing a device design methodology that requires zero process infrastructure changes, a widely available platform for high-performance photonic-electronic integrated circuits is enabled.

© 2012 OSA

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  1. M. Hochberg and T. Baehr-Jones, “Towards fabless silicon photonics,” Nat. Photonics 4(8), 492–494 (2010).
    [CrossRef]
  2. P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).
  3. M. Hochberg, “Fabless nanophotonics,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2011), CWM1.
  4. C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
    [CrossRef]
  5. L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).
  6. Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008).
    [CrossRef]
  7. I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).
  8. W. A. Zortman, D. C. Trotter, A. L. Lentine, G. Robertson, and M. R. Watts, “Monolithic integration of silicon electronics and photonics,” in Winter Topicals (IEEE 2011), 139–140.
  9. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Opt. Express 19(3), 2335–2346 (2011).
    [CrossRef] [PubMed]
  10. S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, and P. Agnello, “High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography,” in International Electron Devices Meeting (IEEE, 2006), 1–4.
  11. J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
    [CrossRef]
  12. B. Jang and A. Hassibi, “Biosensor systems in standard CMOS processes: fact or fiction?” IEEE Trans. Ind. Electron. 56(4), 979–985 (2009).
    [CrossRef]
  13. Akustica, “Technology,” retrieved February 7, 2012, http://www.akustica.com/Technology.asp .
  14. C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
    [CrossRef]
  15. R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
    [CrossRef]
  16. L. Sungjae, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, K. Jonghae, J. O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF performance of 45-nm SOI CMOS Technology,” in Electron Devices Meeting (IEEE 2007), 255–258.
  17. J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010).
    [CrossRef]
  18. J. S. Orcutt, A. Khilo, M. A. Popovic, C. W. Holzwarth, B. Moss, L. Hanqing, M. S. Dahlem, T. D. Bonifield, F. X. Kartner, E. P. Ippen, J. L. Hoyt, R. J. Ram, and V. Stojanovic, “Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2008), CTuBB3.
  19. J. S. Orcutt, “Scaled CMOS photonics,” in Photonics in Switching (Optical Society of America, 2010), PMC4.
  20. S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010).
    [CrossRef] [PubMed]
  21. P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010).
    [CrossRef] [PubMed]
  22. F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007).
    [CrossRef]
  23. S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
    [CrossRef]
  24. M. A. Popovic, T. Barwicz, E. Ippen, and F. X. Kärtner, “Global design rules for silicon microphotonic waveguides: sensitivity, polarization and resonance tunability,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2006), CTuCC1.
  25. M. A. Popovic, Theory and design of high-index-contrast microphotonic circuits (Massachusetts Institute of Technology, 2008).
  26. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
    [CrossRef]
  27. M. Georgas, J. Leu, B. Moss, S. Chen, and V. Stojanovic, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Custom Integrated Circuits Conference (IEEE, 2011), 1–8.
  28. P. Dong, W. Qian, H. Liang, R. Shafiiha, X. Wang, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “1x4 reconfigurable demultiplexing filter based on free-standing silicon racetrack resonators,” Opt. Express 18(24), 24504–24509 (2010).
    [CrossRef] [PubMed]
  29. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A monolithically-integrated optical receiver in standard 45-nm SOI,” in European Solid State Circuits Conference (IEEE, 2011), 407–410.
  30. J. Leu and V. Stojanovic, “Injection-locked clock receiver for monolithic optical link in 45nm SOI,” in Asian Solid State Circuits Conference (IEEE, 2011), 149–152.
  31. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005).
    [CrossRef] [PubMed]
  32. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15(2), 430–436 (2007).
    [CrossRef] [PubMed]
  33. F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. F. Moghadam, Z. Xuezhe, J. E. Cunningham, A. V. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS,” in Symposium on VLSI Circuits (IEEE, 2011), 290–291.
  34. M. R. Watts, W. A. Zortman, D. C. Trotter, R. W. Young, and A. L. Lentine, “Vertical junction silicon microdisk modulators and switches,” Opt. Express 19(22), 21989–22003 (2011).
    [CrossRef] [PubMed]

2012

J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

2011

2010

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

M. Hochberg and T. Baehr-Jones, “Towards fabless silicon photonics,” Nat. Photonics 4(8), 492–494 (2010).
[CrossRef]

R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
[CrossRef]

J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010).
[CrossRef]

S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010).
[CrossRef] [PubMed]

P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010).
[CrossRef] [PubMed]

P. Dong, W. Qian, H. Liang, R. Shafiiha, X. Wang, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “1x4 reconfigurable demultiplexing filter based on free-standing silicon racetrack resonators,” Opt. Express 18(24), 24504–24509 (2010).
[CrossRef] [PubMed]

2009

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

B. Jang and A. Hassibi, “Biosensor systems in standard CMOS processes: fact or fiction?” IEEE Trans. Ind. Electron. 56(4), 979–985 (2009).
[CrossRef]

2008

Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008).
[CrossRef]

2007

2006

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

2005

C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
[CrossRef]

Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005).
[CrossRef] [PubMed]

Ahn, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Apsel, A. B.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Asghari, M.

Baehr-Jones, T.

M. Hochberg and T. Baehr-Jones, “Towards fabless silicon photonics,” Nat. Photonics 4(8), 492–494 (2010).
[CrossRef]

Baets, R.

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

Beals, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Bhave, S. A.

Block, B. A.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Bogaerts, W.

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

Bonifield, T.

Carothers, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Chang, P. L. D.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Chen, Y. K.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Chiu, C.-F.

C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
[CrossRef]

Choi, W.

J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

Conway, T.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Cunningham, J. E.

Dai, C.-L.

C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
[CrossRef]

Dong, P.

Dumon, P.

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

Fedeli, J. M.

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

Feng, D.

Feng, N.-N.

Floyd, M.

R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
[CrossRef]

Fulbert, L.

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

Gill, D. M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Green, W. M. J.

Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008).
[CrossRef]

Grove, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Gunn, C.

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

Hassibi, A.

B. Jang and A. Hassibi, “Biosensor systems in standard CMOS processes: fact or fiction?” IEEE Trans. Ind. Electron. 56(4), 979–985 (2009).
[CrossRef]

Hochberg, M.

M. Hochberg and T. Baehr-Jones, “Towards fabless silicon photonics,” Nat. Photonics 4(8), 492–494 (2010).
[CrossRef]

Hollingsworth, R.

Holzwarth, C. W.

Hong, C. Y.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Jaenen, P.

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

Jang, B.

B. Jang and A. Hassibi, “Biosensor systems in standard CMOS processes: fact or fiction?” IEEE Trans. Ind. Electron. 56(4), 979–985 (2009).
[CrossRef]

Juang, Y.-Z.

C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
[CrossRef]

Kalla, R.

R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
[CrossRef]

Kärtner, F. X.

Kern, A. M.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Khilo, A.

Kimerling, L. C.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Krishnamoorthy, A. V.

Lee, M.

J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

Lentine, A. L.

Li, G.

Li, H.

Liang, H.

Liao, J. T. S.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Lipson, M.

Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” Opt. Express 15(2), 430–436 (2007).
[CrossRef] [PubMed]

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005).
[CrossRef] [PubMed]

Liu, J.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Manipatruni, S.

Michel, J.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

Mohammed, E.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Orcutt, J. S.

Palermo, S.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Pan, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Park, K.

J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

Patel, S. S.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Pomerene, A. T.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Popovic, M. A.

Pradhan, S.

Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005).
[CrossRef] [PubMed]

Qian, W.

Ram, R. J.

Rasras, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Reshotko, M. R.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Schmidt, B.

Sekaric, L.

F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007).
[CrossRef]

Selvaraja, S. K.

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

Shafiiha, R.

Shakya, J.

Sinharoy, B.

R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
[CrossRef]

Smith, H. I.

Sparacin, D. K.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Sridaran, S.

Starke, W. J.

R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
[CrossRef]

Stojanovic, V.

Sun, J.

Thourhout, D. V.

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

Trotter, D. C.

Tu, K. Y.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Vlasov, Y.

Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008).
[CrossRef]

F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007).
[CrossRef]

Wang, X.

Watts, M. R.

White, A. E.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Wong, C. W.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Xia, F.

Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008).
[CrossRef]

Xia, F. N.

F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007).
[CrossRef]

Xiao, F.-Y.

C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
[CrossRef]

Xu, Q.

Youn, J.

J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

Young, I. A.

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

Young, R. W.

Zheng, X.

Zortman, W. A.

Electron. Lett.

P. Dumon, W. Bogaerts, R. Baets, J. M. Fedeli, and L. Fulbert, “Towards foundry approach for silicon photonics: silicon photonics platform ePIXfab,” Electron. Lett. 45, 13–14 (2009).

IEEE J. Quantum Electron.

J. Youn, M. Lee, K. Park, and W. Choi, “A 10-Gb/s 850-nm CMOS OEIC Receiver with a Silicon Avalanche Photodetector,” IEEE J. Quantum Electron. 48(2), 229–236 (2012).
[CrossRef]

IEEE J. Solid-St. Circulation

I. A. Young, E. Mohammed, J. T. S. Liao, A. M. Kern, S. Palermo, B. A. Block, M. R. Reshotko, and P. L. D. Chang, “Optical I/O technology for tera-scale computing,” IEEE J. Solid-St. Circulation 45, 235–248 (2010).

IEEE Micro

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, “Power7: IBM's next-generation server processor,” IEEE Micro 30(2), 7–15 (2010).
[CrossRef]

IEEE Photon. Technol. Lett.

J. S. Orcutt and R. J. Ram, “Photonic device layout within the foundry CMOS design environment,” IEEE Photon. Technol. Lett. 22(8), 544–546 (2010).
[CrossRef]

IEEE Trans. Ind. Electron.

B. Jang and A. Hassibi, “Biosensor systems in standard CMOS processes: fact or fiction?” IEEE Trans. Ind. Electron. 56(4), 979–985 (2009).
[CrossRef]

J. Lightwave Tech.

S. K. Selvaraja, P. Jaenen, W. Bogaerts, D. V. Thourhout, P. Dumon, and R. Baets, “Fabrication of photonic wire and crystal circuits in silicon-on-insulator using 193-nm optical lithography,” J. Lightwave Tech. 27(18), 4076–4083 (2009).
[CrossRef]

J. Micromech. Microeng.

C.-L. Dai, F.-Y. Xiao, Y.-Z. Juang, and C.-F. Chiu, “An approach to fabricating microstructures that incorporate circuits using a post-CMOS process,” J. Micromech. Microeng. 15(1), 98–103 (2005).
[CrossRef]

Nat. Photonics

F. N. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nat. Photonics 1(1), 65–71 (2007).
[CrossRef]

M. Hochberg and T. Baehr-Jones, “Towards fabless silicon photonics,” Nat. Photonics 4(8), 492–494 (2010).
[CrossRef]

Y. Vlasov, W. M. J. Green, and F. Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nat. Photonics 2(4), 242–246 (2008).
[CrossRef]

Nature

Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson, “Micrometre-scale silicon electro-optic modulator,” Nature 435(7040), 325–327 (2005).
[CrossRef] [PubMed]

Opt. Express

Proc. IEEE

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

Proc. SPIE

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y. K. Chen, T. Conway, D. M. Gill, M. Grove, C. Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K. Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Other

M. Hochberg, “Fabless nanophotonics,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2011), CWM1.

W. A. Zortman, D. C. Trotter, A. L. Lentine, G. Robertson, and M. R. Watts, “Monolithic integration of silicon electronics and photonics,” in Winter Topicals (IEEE 2011), 139–140.

S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C. H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, and P. Agnello, “High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography,” in International Electron Devices Meeting (IEEE, 2006), 1–4.

Akustica, “Technology,” retrieved February 7, 2012, http://www.akustica.com/Technology.asp .

J. S. Orcutt, A. Khilo, M. A. Popovic, C. W. Holzwarth, B. Moss, L. Hanqing, M. S. Dahlem, T. D. Bonifield, F. X. Kartner, E. P. Ippen, J. L. Hoyt, R. J. Ram, and V. Stojanovic, “Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2008), CTuBB3.

J. S. Orcutt, “Scaled CMOS photonics,” in Photonics in Switching (Optical Society of America, 2010), PMC4.

L. Sungjae, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, K. Jonghae, J. O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF performance of 45-nm SOI CMOS Technology,” in Electron Devices Meeting (IEEE 2007), 255–258.

M. Georgas, J. Leu, B. Moss, S. Chen, and V. Stojanovic, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Custom Integrated Circuits Conference (IEEE, 2011), 1–8.

M. A. Popovic, T. Barwicz, E. Ippen, and F. X. Kärtner, “Global design rules for silicon microphotonic waveguides: sensitivity, polarization and resonance tunability,” in Conference on Lasers and Electro-Optics (Optical Society of America, 2006), CTuCC1.

M. A. Popovic, Theory and design of high-index-contrast microphotonic circuits (Massachusetts Institute of Technology, 2008).

M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A monolithically-integrated optical receiver in standard 45-nm SOI,” in European Solid State Circuits Conference (IEEE, 2011), 407–410.

J. Leu and V. Stojanovic, “Injection-locked clock receiver for monolithic optical link in 45nm SOI,” in Asian Solid State Circuits Conference (IEEE, 2011), 149–152.

F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. F. Moghadam, Z. Xuezhe, J. E. Cunningham, A. V. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS,” in Symposium on VLSI Circuits (IEEE, 2011), 290–291.

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Figures (8)

Fig. 1
Fig. 1

Illustrated micrograph of the fabricated electronic-photonic integration test die containing 54 independently addressable electronic-photonic test cells. Each digitally interfaced cell contains the pseudorandom bit sequence (PRBS) generators, samplers and comparators necessary for in situ link signal monitoring and bit error rate (BER) testing. Only the transmit end of an electronic-photonic link is reported in this work.

Fig. 2
Fig. 2

Plot of measured logical stage delay for ring oscillators both before and after substrate transfer (described in Section 3) as a function of supply voltage. The nominal supply voltage for this process is 1V. The delay is extracted by dividing the measured oscillation frequency by the number of stages.

Fig. 3
Fig. 3

Cross section cartoon of photonic integration within a scaled thin-SOI platform. The single-crystalline silicon waveguide core (body-Si) is formed in the layer that functions as the transistor body in the standard electronics process. The polysilicon (poly-Si) waveguide core is formed in the layer that functions as the transistor gate in the standard electronics process. The proximity of the two layers enables the formation of a strip-loaded waveguide as well.

Fig. 4
Fig. 4

The waveguide loss was measured in structures with 4.1 mm differential length, analogous to the cut-back method, on four samples. Propagation loss in 470 nm wide waveguides was measured from 1260 nm to 1350 nm (a) and in 700 nm wide waveguides was measured from 1450 nm to 1630 nm (b). Measured fiber-to-fiber transmission spectra of the drop ports of moderately-coupled (red data points) and weakly-coupled (blue data points) 20 μm radius rings at 1280 nm (c) and 1550 nm (d) are fit to coupled resonator models (solid black lines) for intrinsic quality factor extraction. The dip at the center of the resonance results from scattering-induced coupling between the forward and backward propagating ring modes. For the weakly-coupled rings, quality factors of 227,000 and 112,000 were extracted for 1280 nm and 1550 nm respectively. Ring and bus waveguide widths were 470 nm for 1280 nm and 670 nm for 1550 nm. Coupling gaps of 830 nm and 740 nm were used for 1550 nm; 660 nm and 600 nm were used for 1280 nm.

Fig. 5
Fig. 5

(a) Optical micrograph of an 8-channel filter bank implemented with 7.0 μm nominal radius first-order ring-resonator filters. Design dimensions: 470 nm ring and bus waveguide widths, 217 nm input and drop side ring-bus coupling gaps. (b) Filter bank transfer function for all ports as measured for fiber-to-fiber transmission.

Fig. 6
Fig. 6

The aggregate filter bank through port transmission function (a) is measured before and after the heater tuning by the integrated controller (b). Heater output parameters for each channel were programmed into the on-chip controller after measurement of the untuned transmission function. The overlaid drop port characteristics for all 8 channels are shown in (c) to demonstrate less than −20 dB cross talk between adjacent 250 GHz spaced channels across the full 30 GHz channel width for all ports.

Fig. 7
Fig. 7

Resonant electro-optic modulators were demonstrated using rib waveguide, carrier-injection phase shifters. (a) The optical transmission spectra with inset micrographs are shown for the 1280 nm (Q = 3970) and 1550 nm (Q = 4290) wavelength bands. The silicon slab layers are continuous in the coupling regions and 132 nm gaps and 122 nm gaps are formed between the polysilicon strips for the 1280 nm and 1550nm designs respectively. Cross-section cartoon of the 1550 nm device is shown in (b) to illustrate the lateral optical mode confinement, contours, and electrical contact regions. The eye diagram (c) demonstrates 600 Mbps data transmission with 10 dB on-off extinction ratio for the 1550 nm modulator integrated with a modulator driver. The step function time constant dependence on driver configuration (d) demonstrates the acceleration of carrier depletion under reverse bias, but at the expense of the carrier-injection time constant in the current integrated driver configuration for a 1280 nm modulator. The measured small-signal modulation electro-optic transfer response for a 1550 nm modulator is shown in (e) with the injection current as a function of diode bias voltage shown in inset for both modulators (1550 nm device in blue, 1280 nm in red).

Fig. 8
Fig. 8

Configurable, all-digital modulator driver circuit with split supplies and sub-bit pre-emphasis. The final driver stage utilizes split-supply to decouple increased modulator supply voltage from backend digital circuit supply to maintain backend circuit performance for various modulator supply conditions. Configurable forward and reverse bias drive strengths support a variety of modulator device designs on this platform.

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