Abstract

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

© 2012 OSA

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References

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  1. M. Kavehrad, “Sustainable energy-efficient wireless applications using light,” IEEE Commun. Mag. 48(12), 66–73 (2010).
    [CrossRef]
  2. N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
    [CrossRef]
  3. B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
    [CrossRef]
  4. D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
    [CrossRef]
  5. S. Radovanović, A. J. Annema, and B. Nauta, “A 3-Gb/s optical receiver front-end in .18 μm CMOS,” IEEE J. Solid-State Circuits 40(8), 1706–1717 (2005).
  6. F. Tavernier and M. S. J. Steyaert, “High speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-State Circuits 44(10), 2856–2867 (2009).
    [CrossRef]
  7. S. B. Alexander, Optical Communication Receiver Design (SPIE Optical Engineering Press, 1997).
    [CrossRef]
  8. D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron. 4(6), 1040–1045 (1998).
    [CrossRef]
  9. S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
    [CrossRef]
  10. J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
    [CrossRef]
  11. B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw Hill, USA, 2003).
  12. H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.
  13. T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999).
    [CrossRef]
  14. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

2011 (1)

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

2010 (2)

M. Kavehrad, “Sustainable energy-efficient wireless applications using light,” IEEE Commun. Mag. 48(12), 66–73 (2010).
[CrossRef]

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

2009 (2)

F. Tavernier and M. S. J. Steyaert, “High speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

2008 (1)

N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
[CrossRef]

2005 (1)

S. Radovanović, A. J. Annema, and B. Nauta, “A 3-Gb/s optical receiver front-end in .18 μm CMOS,” IEEE J. Solid-State Circuits 40(8), 1706–1717 (2005).

2001 (1)

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

1999 (1)

T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999).
[CrossRef]

1998 (1)

D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron. 4(6), 1040–1045 (1998).
[CrossRef]

Alexander, S. B.

S. B. Alexander, Optical Communication Receiver Design (SPIE Optical Engineering Press, 1997).
[CrossRef]

Annema, A. J.

S. Radovanović, A. J. Annema, and B. Nauta, “A 3-Gb/s optical receiver front-end in .18 μm CMOS,” IEEE J. Solid-State Circuits 40(8), 1706–1717 (2005).

Chang, Y.-W.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

Chen, W.-Z.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

Ciftcioglu, B.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Coppee, D.

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron. 4(6), 1040–1045 (1998).
[CrossRef]

Deen, M. J.

N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
[CrossRef]

Fang, Q.

N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
[CrossRef]

Faramarzpour, N.

N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
[CrossRef]

Genoe, J.

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

Ghazi, A.

H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

Han, G.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Han, J.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Heide, T.

H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

Huang, S.-H.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

Huang, Y.-T.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

Kavehrad, M.

M. Kavehrad, “Sustainable energy-efficient wireless applications using light,” IEEE Commun. Mag. 48(12), 66–73 (2010).
[CrossRef]

Kieschnick, K.

H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

Krishnamoorthy, A. V.

T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999).
[CrossRef]

Kuijk, M.

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron. 4(6), 1040–1045 (1998).
[CrossRef]

Lee, D.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Marciante, J. R.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Nauta, B.

S. Radovanović, A. J. Annema, and B. Nauta, “A 3-Gb/s optical receiver front-end in .18 μm CMOS,” IEEE J. Solid-State Circuits 40(8), 1706–1717 (2005).

Ng, K. K.

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

Park, S. M.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

Radovanovic, S.

S. Radovanović, A. J. Annema, and B. Nauta, “A 3-Gb/s optical receiver front-end in .18 μm CMOS,” IEEE J. Solid-State Circuits 40(8), 1706–1717 (2005).

Razavi, B.

B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw Hill, USA, 2003).

Shirani, S.

N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
[CrossRef]

Sobolewski, R.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Steyaert, M. S. J.

F. Tavernier and M. S. J. Steyaert, “High speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

Stiens, J. H.

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

Sze, S. M.

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

Tavernier, F.

F. Tavernier and M. S. J. Steyaert, “High speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

Vounckx, R.

D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron. 4(6), 1040–1045 (1998).
[CrossRef]

Vounckx, R. A.

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

Woodward, T. K.

T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999).
[CrossRef]

Wu, H.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Zhang, J.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Zhang, L.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Zimmermann, H.

H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

Zuegel, J. D.

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

IEEE Commun. Mag. (1)

M. Kavehrad, “Sustainable energy-efficient wireless applications using light,” IEEE Commun. Mag. 48(12), 66–73 (2010).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron. (2)

T. K. Woodward and A. V. Krishnamoorthy, “1 Gbit/s integrated optical detectors and receivers in commerical CMOS technologies,” IEEE J. Sel. Top. Quantum Electron. 5(2), 146–156 (1999).
[CrossRef]

D. Coppee, M. Kuijk, and R. Vounckx, “Spatially modulated light detector in CMOS with sense-amplifier receiver operating at 180 Mb/s for optical data link applications and parallel optical interconnects between chips,” IEEE J. Sel. Top. Quantum Electron. 4(6), 1040–1045 (1998).
[CrossRef]

IEEE J. Solid-State Circuits (4)

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed Spatially-Modulated photo detector in .18- μm CMOS technology,” IEEE J. Solid-State Circuits 46(5), 1158–1169 (2011).
[CrossRef]

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5 Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45(12), 2861–2873 (2010).
[CrossRef]

S. Radovanović, A. J. Annema, and B. Nauta, “A 3-Gb/s optical receiver front-end in .18 μm CMOS,” IEEE J. Solid-State Circuits 40(8), 1706–1717 (2005).

F. Tavernier and M. S. J. Steyaert, “High speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-State Circuits 44(10), 2856–2867 (2009).
[CrossRef]

IEEE Trans. Electron. Dev. (2)

J. Genoe, D. Coppee, J. H. Stiens, R. A. Vounckx, and M. Kuijk, “Calculation of the current response of the spatially modulated light CMOS detector” IEEE Trans. Electron. Dev. 48(9), 1892–1902 (2001).
[CrossRef]

N. Faramarzpour, M. J. Deen, S. Shirani, and Q. Fang, “Fully integrated single photon avalanche diode detector in standard CMOS .18 μm technology,” IEEE Trans. Electron. Dev. 55(3), 760–767 (2008).
[CrossRef]

J. Lightwave Technol (1)

B. Ciftcioglu, J. Zhang, L. Zhang, J. R. Marciante, J. D. Zuegel, R. Sobolewski, and H. Wu, “Integrated silicon PIN photodiodes using deep N-Well in a standard .18 mum CMOS technology,” J. Lightwave Technol.  27(15), 3303–3313 (2009).
[CrossRef]

Other (4)

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (John Wiley and Sons, NJ. USA, 2007).

B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw Hill, USA, 2003).

H. Zimmermann, K. Kieschnick, T. Heide, and A. Ghazi, “Integrated high-speed, high-responsivity Photodiode in CMOS and BiCMOS technology,” in Proceeding of the 29th. European Solid-State Device Research Conference, (Feb. 1999), 332–335.

S. B. Alexander, Optical Communication Receiver Design (SPIE Optical Engineering Press, 1997).
[CrossRef]

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Figures (16)

Fig. 1
Fig. 1

Illustration of absorbed light and generated carriers in different regions of a Si-CMOS photodiode (α is absorption coefficient).

Fig. 2
Fig. 2

Photo-generated current response of CMOS photodiodes, (a) time domain, (b) frequency domain.

Fig. 3
Fig. 3

Extending the bandwidth of photodiode by cancelling the diffusive component, (a) ideal cancellation, (b) partial cancellation through modified device structure (addition of equalizer diode), and (c) combined device and circuit level equalization.

Fig. 4
Fig. 4

(a) Structure of Spatially Modulated Light (SML) detector, (b) schematic of SML and connection to the following amplifier.

Fig. 5
Fig. 5

Contours of diffusive electron currents inside the substrate for SML photodiode, (a) electron concentration, (b) current densities.

Fig. 6
Fig. 6

(a)Structure of Double PD, (b) equivalent circuit and connection to the amplifier.

Fig. 7
Fig. 7

Contours of diffusive electrons of substrate and their path in Double PD, (a) electron concentration, (b) current densities.

Fig. 8
Fig. 8

(a) Interrupted P- Finger photodiode, (b) equivalent circuit and connection to the amplifier.

Fig. 9
Fig. 9

(a)Triple well Interrupted N-Finger photodiode, (b)equivalent circuit and connection to the amplifier.

Fig. 10
Fig. 10

Contours of diffusive electron current of substrate inside a Triple well Interrupted N-Finger photodiode, (a)electron concentration, (b) current densities.

Fig. 11
Fig. 11

Frequency Response of SML photodiode (W=6 μm, S= 2.2μm), area = 65×65μm2 at λ = 850nm.

Fig. 12
Fig. 12

Frequency response of Double photodiode (LN–Well = 45μm, LP+ = 25μm), with total size of 65μm × 65μm for two different wavelengths.

Fig. 13
Fig. 13

Simulation results for a 3 finger Interrupted P-Finger photodiode (LN–Well = 45μm, W = 4μm, and S = 4μm), with total size of 65μm × 65μm.

Fig. 14
Fig. 14

Simulated frequency response of a Triple-Well 3 finger Interrupted N-Finger photodiode (LN–Well = 45μm, LP–Well = 25μm, W = 3μm, and S = 1.4μm), in response to 850 and 600 nm wavelengths.

Fig. 15
Fig. 15

General structure of 130 nm technology with Back end of line metallization and dielectric stack.

Fig. 16
Fig. 16

Transmittance of light passing through the stack of dielectric layers in 130 nm IBM CMOS technology with ±20% process variation in thickness of layers.

Tables (1)

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Table 1 Performance parameters comparison of high speed CMOS photodiodes.

Equations (5)

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ω t = 2.78 τ t
= I Photo P Absorbed = I Photo P Shined ( 1 R ) T
f 3 d B 2 π D n 3 ( ( 1 S ) 2 + ( 1 L n ) 2 )
I n 2 = 2 q I Dark Δ f
F O M = ( R [ m A W ] × B . W . [ M H z ] C [ P F ] × I Leakage [ p A ] × ( Technology 2 [ n m 2 ] ) ) × 1000

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