Abstract

This paper proposes a new hardware architecture to speed-up the digital hologram calculation by parallel computation. To realize it, we modify the computer-generated hologram (CGH) equation and propose a cell-based very large scale integrated circuit architecture. We induce a new equation to calculate the horizontal or vertical hologram pixel values in parallel, after finding the calculation regularity in the horizontal or vertical direction from the basic CGH equation. We also propose the architecture of the computer-generated hologram cell consisting of an initial parameter calculator and update-phase calculators based on the equation, and then implement them in hardware. Modifying the equation could simplify the hardware, and approximating the cosine function could optimize the hardware. In addition, we show the hardware architecture to parallelize the calculation in the horizontal direction by extending computer-generated holograms. In the experiments, we analyze hardware resource usage and the performance-capability characteristics of the look-up table used in the computer-generated hologram cell. These analyses make it possible to select the amount of hardware to the precision of the results. Here, we used the platform from our previous work for the computer-generated hologram kernel and the structure of the processor.

© 2011 OSA

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References

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  1. S. Benton and V. M. Bove, Holographic Imaging (Wiley, 2008).
    [CrossRef]
  2. J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).
  3. P. Hariharan, Basics of Holography (Cambridge University Press, 2002).
    [CrossRef]
  4. M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
    [CrossRef]
  5. H. Yoshikawa, S. Iwase, and T. Oneda, “Fast computation of fresnel holograms employing differences,” Proc. SPIE 3956, 48–55 (2000).
    [CrossRef]
  6. T. Shimobaba and T. Ito, “An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition,” Comput. Phys. Commun. 138, 44–52 (2001).
    [CrossRef]
  7. T. Ito, N. Masuda, K. Yoshimura, A. Shiraki, T. Shimobaba, and T. Sugie, “Special-purpose computer HORN-5 for a real-time electroholography,” Opt. Express 13, 1923–1932 (2005).
    [CrossRef] [PubMed]
  8. Y. Ichihashi, H. Nakayama, T. Ito, N Masuda, T. Shimobaba, A Shiraki, and T. Sugie, “HORN-6 special-purpose clustered computing system for electroholography,” Opt. Express 17, 13895–13903 (2009).
    [CrossRef] [PubMed]
  9. Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
    [CrossRef]
  10. N. Masuda, T. Ito, T. Tanaka, A. Shiraki, and T. Sugie, “Computer generated holography using a graphics processing unit,” Opt. Express 14, 603–608 (2006).
    [CrossRef] [PubMed]
  11. L. Ahrenberg, P. Benzie, M. Magnor, and J. Watson, “Computer generated holography using parallel commodity graphics hardware,” Opt. Express 14, 7636–7641 (2006).
    [CrossRef] [PubMed]
  12. Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
    [CrossRef]
  13. Y.-Z. Liu, J.-W. Dong, Y.-Y. Pu, B.-C. Chen, H.-X. He, and H.-Z. Wang, “High-speed full analytical holographic computations for true-life scenes,” Opt. Express 18, 3345–3351 (2010).
    [CrossRef] [PubMed]
  14. T. Shimobaba, T. Ito, N Masuda, Y Ichihashi, and N. Takada, “Fast calculation of computer-generated-hologram on AMD HD5000 series GPU and OpenCL,” Opt. Express 18, 9955–9960 (2010).
    [CrossRef] [PubMed]
  15. W. G. Joseph, Introduction to Fourier Optics , 3rd ed. (Roberts and Company, 2005).

2010

2009

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Y. Ichihashi, H. Nakayama, T. Ito, N Masuda, T. Shimobaba, A Shiraki, and T. Sugie, “HORN-6 special-purpose clustered computing system for electroholography,” Opt. Express 17, 13895–13903 (2009).
[CrossRef] [PubMed]

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
[CrossRef]

2006

2005

2001

T. Shimobaba and T. Ito, “An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition,” Comput. Phys. Commun. 138, 44–52 (2001).
[CrossRef]

2000

H. Yoshikawa, S. Iwase, and T. Oneda, “Fast computation of fresnel holograms employing differences,” Proc. SPIE 3956, 48–55 (2000).
[CrossRef]

1993

M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
[CrossRef]

Ahrenberg, L.

Benton, S.

S. Benton and V. M. Bove, Holographic Imaging (Wiley, 2008).
[CrossRef]

Benzie, P.

Bin, R.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Bove, V. M.

S. Benton and V. M. Bove, Holographic Imaging (Wiley, 2008).
[CrossRef]

Chen, B.-C.

Choi, H.-J.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
[CrossRef]

Chong, T.-C.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Chung, J. K.

J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).

Dong, J.-W.

Hariharan, P.

P. Hariharan, Basics of Holography (Cambridge University Press, 2002).
[CrossRef]

He, H.-X.

Ichihashi, Y

Ichihashi, Y.

Ito, T.

Iwase, S.

H. Yoshikawa, S. Iwase, and T. Oneda, “Fast computation of fresnel holograms employing differences,” Proc. SPIE 3956, 48–55 (2000).
[CrossRef]

Joseph, W. G.

W. G. Joseph, Introduction to Fourier Optics , 3rd ed. (Roberts and Company, 2005).

Kim, D.-W.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
[CrossRef]

Liang, X.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Liu, Y.-Z.

Lucente, M.

M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
[CrossRef]

Magnor, M.

Masuda, N

Masuda, N.

Nakayama, H.

Oneda, T.

H. Yoshikawa, S. Iwase, and T. Oneda, “Fast computation of fresnel holograms employing differences,” Proc. SPIE 3956, 48–55 (2000).
[CrossRef]

Pan, Y.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Pu, Y.-Y.

Seo, Y.-H.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
[CrossRef]

Shimobaba, T.

Shiraki, A

Shiraki, A.

Solanki, S.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Sugie, T.

Takada, N.

Tan, C.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Tanaka, T.

Tanjung, A.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Tsai, M. H.

J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).

Wang, H.-Z.

Watson, J.

Xu, X.

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Yoo, J.-S.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
[CrossRef]

Yoshikawa, H.

H. Yoshikawa, S. Iwase, and T. Oneda, “Fast computation of fresnel holograms employing differences,” Proc. SPIE 3956, 48–55 (2000).
[CrossRef]

Yoshimura, K.

Comput. Phys. Commun.

T. Shimobaba and T. Ito, “An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition,” Comput. Phys. Commun. 138, 44–52 (2001).
[CrossRef]

J. Electron. Imaging

M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
[CrossRef]

J. Syst. Archit.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2009).
[CrossRef]

Opt. Express

Optics Express

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Optics Express 17, 18543–18555 (2009).
[CrossRef]

Proc. SPIE

H. Yoshikawa, S. Iwase, and T. Oneda, “Fast computation of fresnel holograms employing differences,” Proc. SPIE 3956, 48–55 (2000).
[CrossRef]

Other

S. Benton and V. M. Bove, Holographic Imaging (Wiley, 2008).
[CrossRef]

J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).

P. Hariharan, Basics of Holography (Cambridge University Press, 2002).
[CrossRef]

W. G. Joseph, Introduction to Fourier Optics , 3rd ed. (Roberts and Company, 2005).

Supplementary Material (2)

» Media 1: MOV (250 KB)     
» Media 2: MOV (2190 KB)     

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Figures (8)

Fig. 1
Fig. 1

Calculating a row of hologram components by one object light source.

Fig. 2
Fig. 2

Architecture of CGH cells: (a) initial-parameter calculator, (b) update-phase calculator.

Fig. 3
Fig. 3

The pipelined architecture of the update-phase calculator.

Fig. 4
Fig. 4

Extension of update-phase calculator for pixel-based parallelization; (a) extendable structure with sequential outputs, (b) extendable structure with sequential or parallel outputs.

Fig. 5
Fig. 5

The experimental results of approximation for the cosine function; (a) hologram (b) reconstructed object.

Fig. 6
Fig. 6

The object reconstruction results for the approximations of cosine function by assigning; (a) 0 bit, (b) 1 bit, (c) 15 bits, (d) 30 bits.

Fig. 7
Fig. 7

Calculation speed according to the amount of hardware.

Fig. 8
Fig. 8

Examples of reconstructed images (upper ones for Ballet and the lower ones for Hyun-Jin); (a) and (d) depth maps, (b) and (e) reconstructed results by software, (c) and (f) (Media 1) and (Media 2) reconstructed results by optical apparatus for the CGH generated by the proposed hardware.

Tables (3)

Tables Icon

Table 1 Pipeline Stage Scheduling

Tables Icon

Table 2 Hardware Resource of CGH Cell

Tables Icon

Table 3 Performances for Various Implementation Conditions

Equations (19)

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I α j = A j cos ( k ( p x α p x j ) 2 + ( p y α p y j ) 2 + z j 2 + Φ α + Φ j )
I α j A j cos [ 2 π { z j λ + p 2 2 λ z j ( x α j 2 + y α j 2 ) } + Φ α + Φ j ] = A j cos [ θ ( x α j , y α j , z j ) + Φ α + Φ j ]
θ H ( x α j , y α j , z j ) = 2 π [ z j λ + p 2 2 λ z j ( x α j 2 + y α j 2 ) ] = 2 π ( θ Z + θ XY )
θ Z ( z j ) = z j λ
θ XY ( x α j , y α j , z α j ) = p 2 2 λ z j ( x α j 2 + y α j 2 )
θ XY ( x α j + d , y α j , z α j ) = p 2 2 λ z j ( x α j 2 + y α j 2 ) + p 2 2 λ z j ( 2 d x α j 2 + d 2 ) = θ XY ( x α j , y α j , z j ) + p 2 2 λ z j ( 2 d x α j 2 + d 2 )
I α j , d = 0 = A j cos [ 2 π { θ Z + θ XY , d = 0 } + Φ α + Φ j ]
I α j , d 1 = A j cos [ 2 π { θ Z + θ XY , d = 0 + Γ d } + Φ α + Φ j ]
θ XY , d = 0 ( x = 0 ) = p 2 2 λ z j ( x α j 2 + y α j 2 )
Γ d = Γ d 1 + Γ 1 + ( d 1 ) Δ , ( d 1 )
Γ 1 ( x α j , z j ) = p 2 2 λ z j ( 2 x α j + 1 )
Δ = p 2 λ z j
Γ 1 ( x α j , z j ) = p 2 2 λ z j ( 2 x α j + 1 ) = 1 Γ 1 + 0 Δ Γ 2 ( x α j , z j ) = p 2 2 λ z j ( 4 x α j + 4 ) = 2 Γ 1 + 1 Δ Γ 3 ( x α j , z j ) = p 2 2 λ z j ( 6 x α j + 9 ) = 3 Γ 1 + 3 Δ Γ 4 ( x α j , z j ) = p 2 2 λ z j ( 8 x α j + 16 ) = 4 Γ 1 + 6 Δ
Γ d ( x α j , z j ) = p 2 2 λ z j ( 2 d x α j + d 2 ) = d [ Γ 1 + 1 2 ( d 1 ) Δ ] ( d 1 )
i init ( x α j , y α j , z j ) = ( θ H , d = 0 = θ Z + θ XY , d = 0 , Γ 1 , Δ )
i update ( i init ( ) , d ) = ( θ H , d 1 = θ Z + θ XY , d = 0 , Γ d )
PSNR ( d B ) = 10 log 10 225 2 1 XY Σ x , y ( I x , y I x , y ) 2
NC = Σ j = 1 XY I j I j Σ j = 1 XY I j 2
Calculation speed ( clock speed ) × ( amount of implemented hardware ) ( number of object points ) × ( hologram    resolution )

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