V. C. Venugopal and A. J. Perry, “Method for in-situ monitoring of patterned substrate processing using reflectometry,” US patent 7019844.
M. Bass, Handbook of Optics, 3rd ed. (McGraw-Hill, 2009) Vol. 4.
K. C. Huang, “The study of high aspect ratio TSV metrology,” master thesis, National Tsing Hua University, 2010.
ITRS Metrology 2007 ed.2007.
ITRS Assembly & Packaging2009.
H. Singh, C. Rusu, and V. Vahedi, “Etch challenges for 3-D integration,” 3rd Workshop on Plasma Etch and Strip in Microelectronics 2010, Grenoble, France.
M. Puech, J. M. Thevenoud, J. M. Gruffat, N. Launay, N. Arnal, and P. Godinat, “Fabrication of 3D packaging TSV using DRIE,” Symposium on Design, Test, Integrate ion and Packaging of MEMS/MOEMS, 2008.
W. H. Teh, R. Caramto, J. Qureshi, S. Arkalgud, M. O’Brien, T. Gilday, K. Maekawa, T. Saito, K. Maruyama, T. Chidambaram, W. Wang, D. Marx, D. Grant, and R. Dudley, “A route towards production-worthy 5 μm x 25 μm and 1 μm x 20 μm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration,” IEEE 3DIC Conference, 2009.
F. Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, K.-N. Chen, X. Li, D. A. Dipaola, D. Brown, C. T. Ryan, J. A. Hagan, K. H. Wong, M. Lu, X. Gu, N. R. Klymko, E. D. Perfecto, A. G. Merryman, K. A. Kelly, S. Purushothaman, S. J. Koester, R. Wisnieff, and W. Haensch, “A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding,” Proc. International Electron Devices Meeting (IEDM) (2008) p. 599.
M. Puech, J. M. Thevenoud, and J. M. Gruffat, “DRIE for MEMS devices,” Advanced Packaging, 2008.
D. Marx, D. Grant, R. Dudley, A. Rudack, and W. H. Teh, “Wafer thickness sensor (WTS) for etch depth measurement of TSV,” IEEE International Conference on 3D System Integration, 2009.
M. Knowles, “Optical metrology for TSV process control,” 3D Interconnect Metrology at SEMATECH Workshop during SEMICON West 2009.