D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]
A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]
N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[Crossref]
[PubMed]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[Crossref]
[PubMed]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[Crossref]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[Crossref]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[Crossref]
A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[Crossref]
A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[Crossref]
T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
[Crossref]
T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[Crossref]
N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[Crossref]
[PubMed]
M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
[Crossref]
[PubMed]
R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[Crossref]
L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008).
[Crossref]
[PubMed]
L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[Crossref]
[PubMed]
R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[Crossref]
D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[Crossref]
A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[Crossref]
C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.
H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).
A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).
H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).
Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).