Abstract

We experimentally demonstrate a spatially non-blocking five-port optical router, which is based on microring resonators tuned through the thermo-optic effect. The characteristics of the microring-resonator-based switching element are investigated to achieve balanced performances in its two output ports. The optical router is fabricated on the SOI platform using standard CMOS processing. The effective footprint of the device is about 440×660 μm2. The microring resonators have 3-dB bandwidths of larger than 0.31 nm (38 GHz), and extinction ratios of better than 21 dB for through ports and 16 dB for drop ports. Finally, 12.5 Gbps high-speed signal transmission experiments verify the routing functionality of the optical router.

© 2011 OSA

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  1. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
    [CrossRef]
  2. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
    [CrossRef]
  3. T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kartner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects,” J. Opt. Netw. 6(1), 63–73 (2007).
    [CrossRef]
  4. H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).
  5. N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
    [CrossRef] [PubMed]
  6. M. Yang, W. M. J. Green, S. Assefa, J. Van Campenhout, B. G. Lee, C. V. Jahnes, F. E. Doany, C. L. Schow, J. A. Kash, and Y. A. Vlasov, “Non-blocking 4×4 electro-optic silicon switch for on-chip photonic networks,” Opt. Express 19(1), 47–54 (2011).
    [CrossRef] [PubMed]
  7. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
    [CrossRef]
  8. A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
    [CrossRef]
  9. A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
    [CrossRef]
  10. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.
  11. H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).
  12. A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).
  13. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
    [CrossRef]
  14. D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
    [CrossRef]
  15. A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
    [CrossRef]
  16. Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).
  17. L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
    [CrossRef] [PubMed]
  18. T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
    [CrossRef]
  19. L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008).
    [CrossRef] [PubMed]

2011 (2)

2010 (2)

L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[CrossRef] [PubMed]

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

2009 (2)

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

2008 (5)

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[CrossRef] [PubMed]

L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008).
[CrossRef] [PubMed]

2007 (2)

2004 (1)

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Agarwal, A.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Assefa, S.

Baba, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Baets, R.

Bao, L. W.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Barwicz, T.

Beausoleil, R. G.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Bergman, K.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[CrossRef] [PubMed]

Bianco, A.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Biberman, A.

Borkar, N.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Borkar, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Brown, J. F.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Byun, H.

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Chen, H.

R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[CrossRef]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Chen, L.

Chen, P.

Chin, M. K.

Cuda, D.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Dighe, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Ding, J.

Doany, F. E.

Dumon, P.

Edwards, B.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Erraguntla, V.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Fang, Q.

Finan, D.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Fukazawa, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Gan, F.

Gaudino, R.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Gavilanes, G.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Geis, M.

Green, W. M. J.

Grein, M.

Griffin, P.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Hirano, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Hoffmann, H.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Holzwarth, C. W.

Hoskote, Y.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Howard, J.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Hoyt, J. L.

Ippen, E. P.

Jacob, T.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Jahnes, C. V.

Jain, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Ji, R.

Ji, R. Q.

Jia, L. X.

Jiang, Z. Y.

Kartner, F. X.

Kash, J. A.

Kuekes, P. J.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Lee, B. G.

Lipson, M.

Liu, Y. L.

Lu, Y.

Lu, Y. Y.

Luo, X.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Lyszczarz, T.

Mattina, M.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Miao, C. C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

Neri, F.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Ohno, F.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Olubuyide, O. O.

Orcutt, J. S.

Petracca, M.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Poon, A. W.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Popovic, M. A.

Rakich, P. T.

Ram, R. J.

Ramey, C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Roberts, C.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Ruhl, G.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Schow, C. L.

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Sherwood-Droz, N.

Singh, A.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Smith, H. I.

Snider, G. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Spector, S.

Stojanovic, V.

Tian, Y.

Tian, Y. H.

Tobing, L. Y. M.

Tschanz, J.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Van Campenhout, J.

Vangal, S. R.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Vlasov, Y. A.

Wang, H.

Wang, S.-Y.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Watts, M. R.

Wentzlaff, D.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Williams, R. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Wilson, H.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Xu, F.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Yang, L.

Yang, M.

Yoon, J. U.

Yu, M. B.

Zhang, L.

Zhou, P.

Zhu, W.

IEEE J. Solid-state Circuits (1)

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

IEEE Micro (1)

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

IEEE Photon. Technol. Lett. (1)

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

J. Opt. Netw. (1)

Jpn. J. Appl. Phys. (1)

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Opt. Express (3)

Opt. Lett. (2)

Proc. IEEE (3)

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Other (5)

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor-to-DRAM networks with monolithic silicon photonics,” High-Performance Interconnects, Symposium on, pp. 21–30, 16th IEEE Symposium on High Performance Interconnects, 2008.

H. X. Gu, J. Xu, and W. Zhang, “A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip,” Design, Automation & Test in Europe Conference & Exhibition, 3–8 (2009).

A. Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, “Silicon-photonic clos networks for global on-chip communication,” 2009 3rd Acm/Ieee International Symposium on Networks-on-Chip, 124–133 (2009).

H. X. Gu, K. H. Mo, J. Xu, and W. Zhang, “A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip,” 2009 IEEE Computer Society Annual Symposium on VlSI, 19–24 (2009).

Y. Xie, N. Mahdi, J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu, “Crosstalk noise and bit error rate analysis for optical network-on-chip,” 47th ACM/EDAC/IEEE Design Automation Conference, 657–660 (2010).

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Figures (9)

Fig. 1
Fig. 1

Schematics of 2D photonic mesh (a) and torus (b) networks for 16-core CMPs. (c) A five-port bidirectional optical router. Blue square indicates processing core, yellow dot indicates optical router, and line with arrow indicates optical waveguide.

Fig. 2
Fig. 2

Schematic layout of the five-port non-blocking on-chip optical router.

Fig. 3
Fig. 3

(a) and (b) Configurations of microring-resonator-based switching element at OFF state and On state. (c) Normalized transmissions at the through and drop ports. The black dashed line indicates the operation wavelength. Here, the MRR has a radius of 10 μm, loss of 10 dB/cm and coupling coefficient of 0.35. (d) The variation of extinction ratios for through and drop ports with the coupling coefficient.

Fig. 4
Fig. 4

Micrograph of the five-port optical router based on cascaded MRRs.

Fig. 5
Fig. 5

Spectrum responses of the MRRs labeled as R11, R1, R7, R6, R5 and R4 respectively.

Fig. 6
Fig. 6

Transmission spectra involving four resonance peaks of drop ports for MRRs labeled as R11, R1, R7, R6, R5 and R4 in ON state.

Fig. 7
Fig. 7

Response spectra from the North input port to West output port (black line) and from West input port to North output port (red line).

Fig. 8
Fig. 8

The 12.5 Gbps eye diagrams for an optical signal at the output ports for eight optical paths between West port and other four ports.

Fig. 9
Fig. 9

The 12.5 Gbps BER curves for the signals transmitted between West port and other three ports. A PRBS pattern with a length of 231-1 is used for the BER tests. The back-to-back BER curve is measured by replacing the chip with a variable optical attenuator mimicking the insertion loss induced by the chip.

Tables (1)

Tables Icon

Table 1 Twenty Optical Links of the Five-Port Non-Blocking Optical Router

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