Abstract

We experimentally demonstrate a spatially non-blocking five-port optical router, which is based on microring resonators tuned through the thermo-optic effect. The characteristics of the microring-resonator-based switching element are investigated to achieve balanced performances in its two output ports. The optical router is fabricated on the SOI platform using standard CMOS processing. The effective footprint of the device is about 440×660 μm2. The microring resonators have 3-dB bandwidths of larger than 0.31 nm (38 GHz), and extinction ratios of better than 21 dB for through ports and 16 dB for drop ports. Finally, 12.5 Gbps high-speed signal transmission experiments verify the routing functionality of the optical router.

© 2011 OSA

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2011

2010

L. Zhang, R. Q. Ji, L. X. Jia, L. Yang, P. Zhou, Y. H. Tian, P. Chen, Y. Y. Lu, Z. Y. Jiang, Y. L. Liu, Q. Fang, and M. B. Yu, “Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators,” Opt. Lett. 35(10), 1620–1622 (2010).
[CrossRef] [PubMed]

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

2009

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

2008

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[CrossRef] [PubMed]

L. Y. M. Tobing, P. Dumon, R. Baets, and M. K. Chin, “Boxlike filter response based on complementary photonic bandgaps in two-dimensional microresonator arrays,” Opt. Lett. 33(21), 2512–2514 (2008).
[CrossRef] [PubMed]

2007

2004

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Agarwal, A.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Assefa, S.

Baba, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Baets, R.

Bao, L. W.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Barwicz, T.

Beausoleil, R. G.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Bergman, K.

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4×4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express 16(20), 15915–15922 (2008).
[CrossRef] [PubMed]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Bianco, A.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Biberman, A.

Borkar, N.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Borkar, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Brown, J. F.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Byun, H.

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Chen, H.

R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19(20), 18945–18955 (2011).
[CrossRef]

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Chen, L.

Chen, P.

Chin, M. K.

Cuda, D.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Dighe, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Ding, J.

Doany, F. E.

Dumon, P.

Edwards, B.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Erraguntla, V.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Fang, Q.

Finan, D.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Fukazawa, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Gan, F.

Gaudino, R.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Gavilanes, G.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Geis, M.

Green, W. M. J.

Grein, M.

Griffin, P.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Hirano, T.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Hoffmann, H.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Holzwarth, C. W.

Hoskote, Y.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Howard, J.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Hoyt, J. L.

Ippen, E. P.

Jacob, T.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Jahnes, C. V.

Jain, S.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Ji, R.

Ji, R. Q.

Jia, L. X.

Jiang, Z. Y.

Kartner, F. X.

Kash, J. A.

Kuekes, P. J.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Lee, B. G.

Lipson, M.

Liu, Y. L.

Lu, Y.

Lu, Y. Y.

Luo, X.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Lyszczarz, T.

Mattina, M.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Miao, C. C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97(7), 1166–1185 (2009).
[CrossRef]

Neri, F.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Ohno, F.

T. Fukazawa, T. Hirano, F. Ohno, and T. Baba, “Low loss intersection of Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(2), 646–647 (2004).
[CrossRef]

Olubuyide, O. O.

Orcutt, J. S.

Petracca, M.

A. Bianco, D. Cuda, R. Gaudino, G. Gavilanes, F. Neri, and M. Petracca, “Scalability of optical interconnects based on microring resonators,” IEEE Photon. Technol. Lett. 22(15), 1081–1083 (2010).
[CrossRef]

Poon, A. W.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Popovic, M. A.

Rakich, P. T.

Ram, R. J.

Ramey, C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Roberts, C.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Ruhl, G.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Schow, C. L.

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Sherwood-Droz, N.

Singh, A.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Smith, H. I.

Snider, G. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Spector, S.

Stojanovic, V.

Tian, Y.

Tian, Y. H.

Tobing, L. Y. M.

Tschanz, J.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Van Campenhout, J.

Vangal, S. R.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Vlasov, Y. A.

Wang, H.

Wang, S.-Y.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Watts, M. R.

Wentzlaff, D.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. W. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-chip interconnection architecture of the tile processor,” IEEE Micro 27(5), 15–31 (2007).
[CrossRef]

Williams, R. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Wilson, H.

S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE J. Solid-state Circuits 43(1), 29–41 (2008).
[CrossRef]

Xu, F.

A. W. Poon, X. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97(7), 1216–1238 (2009).
[CrossRef]

Yang, L.

Yang, M.

Yoon, J. U.

Yu, M. B.

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