Abstract
In this work, we report a CMOS comparable fabrication process of core-shell SiNW solar cell from single-crystalline p-type Si(100) test wafers. Optical lithography defined plasma etching was used to form highly ordered vertical SiNW arrays, which display a drastic reduction in optical reflectance over a wide range of wavelengths. BF2 and P ion implantations were employed for producing a sharp and shallow radial p-n junction. Under AM 1.5G illumination, the device demonstrates a short circuit current density (Jsc) of 14.2 mA/cm2, an open circuit voltage (Voc) of 0.485 V and a fill factor (FF) of 42.9%, giving a power conversion efficiency (PCE) of 2.95%. The Jsc observed is 52% higher than that in the control device with planar Si p-n junction, indicating significant enhancement in carrier generation and collection efficiency from the core-shell structure. Impact of series resistance (Rs) is also studied, highlighting potential improvement of PCE to 4.40% in the absence of Rs. With top contact optimized, PCE could further increase to 6.29%.
©2011 Optical Society of America
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