R. Koh, “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999).
T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
J. M. Fedeli, M. Migette, L. Cioccio, L. El Melhaoui, R. Orobtchouk, C. Seassal, P. Rojo-Romeo, F. Mandorlo, D. Marris-Morini, and L. Vivien, “Incorporation of a Photonic Layer at the Metallizations Levels of a CMOS Circuit,” in Group IV Photonics, 2006. 3rd IEEE International Conference on(2006), pp. 200–202.
F. Y. Gardes, G. T. Reed, A. P. Knights, G. Mashanovich, P. E. Jessop, L. Rowe, S. McFaul, D. Bruce, and N. G. Tarr, “Sub-micron optical waveguides for silicon photonics formed via the local oxidation of silicon (LOCOS),” in Silicon Photonics III(SPIE, San Jose, CA, USA, 2008), pp. 68980R–68984.
C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” (IEEE Computer Society Press, 2009), pp. 8–21.
C. W. Holzwarth, J. S. Orcutt, L. Hanqing, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Lasers and Electro-Optics, 2008 and 2008 Conference on Quantum Electronics and Laser Science. CLEO/QELS 2008.(2008), pp. 1–2.
D. Andriukaitis, and R. Anilionis, “Thermal Oxidation in LOCOS, PBL, and SWAMI Micro and nano Structures,” (2007), p. 75.
A. Shacham, K. Bergman, and L. P. Carloni, “On the Design of a Photonic Network-on-Chip,” in Networks-on-Chip(2007), pp. 53–64.