Abstract

We demonstrate a bulk silicon alternative to the conventional silicon-on-insulator photonics platform, using common CMOS process-based Si3N4 masking and oxidation techniques. We show waveguide losses as low as 2.92 dB/cm with a technique that can be implemented on the front-end of a typical CMOS fabrication line.

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References

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  1. A. Shacham, K. Bergman, and L. P. Carloni, “On the Design of a Photonic Network-on-Chip,” in Networks-on-Chip(2007), pp. 53–64.
  2. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
    [CrossRef]
  3. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” (IEEE Computer Society Press, 2009), pp. 8–21.
  4. R. Koh, “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999).
    [CrossRef]
  5. C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
    [CrossRef]
  6. J. M. Fedeli, M. Migette, L. Cioccio, L. El Melhaoui, R. Orobtchouk, C. Seassal, P. Rojo-Romeo, F. Mandorlo, D. Marris-Morini, and L. Vivien, “Incorporation of a Photonic Layer at the Metallizations Levels of a CMOS Circuit,” in Group IV Photonics, 2006. 3rd IEEE International Conference on(2006), pp. 200–202.
  7. F. Y. Gardes, G. T. Reed, A. P. Knights, G. Mashanovich, P. E. Jessop, L. Rowe, S. McFaul, D. Bruce, and N. G. Tarr, “Sub-micron optical waveguides for silicon photonics formed via the local oxidation of silicon (LOCOS),” in Silicon Photonics III(SPIE, San Jose, CA, USA, 2008), pp. 68980R–68984.
  8. R. Pafchek, R. Tummidi, J. Li, M. A. Webster, E. Chen, and T. L. Koch, “Low-loss silicon-on-insulator shallow-ridge TE and TM waveguides formed using thermal oxidation,” Appl. Opt. 48(5), 958–963 (2009).
    [CrossRef] [PubMed]
  9. C. W. Holzwarth, J. S. Orcutt, L. Hanqing, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Lasers and Electro-Optics, 2008 and 2008 Conference on Quantum Electronics and Laser Science. CLEO/QELS 2008.(2008), pp. 1–2.
  10. D. Andriukaitis, and R. Anilionis, “Thermal Oxidation in LOCOS, PBL, and SWAMI Micro and nano Structures,” (2007), p. 75.
  11. V. R. Almeida, R. R. Panepucci, and M. Lipson, “Nanotaper for compact mode conversion,” Opt. Lett. 28(15), 1302–1304 (2003).
    [CrossRef] [PubMed]
  12. T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
    [CrossRef]

2009 (1)

2008 (1)

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

2004 (1)

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

2003 (1)

1999 (1)

R. Koh, “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999).
[CrossRef]

1978 (1)

T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
[CrossRef]

Almeida, V. R.

Ando, R.

T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
[CrossRef]

Beausoleil, R. G.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Boeuf, F.

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

Carriere, N.

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

Chen, E.

Enomoto, T.

T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
[CrossRef]

Fenouillet-Beranger, C.

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

Koch, T. L.

Koh, R.

R. Koh, “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999).
[CrossRef]

Kuekes, P. J.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Li, J.

Lipson, M.

Monfray, S.

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

Morita, H.

T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
[CrossRef]

Nakayama, H.

T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
[CrossRef]

Pafchek, R.

Panepucci, R. R.

Shih-Yuan, W.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Skotnicki, T.

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

Snider, G. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Tummidi, R.

Webster, M. A.

Williams, R. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Appl. Opt. (1)

Jpn. J. Appl. Phys. (2)

R. Koh, “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys. 38(Part 1, No. 4B), 2294–2299 (1999).
[CrossRef]

T. Enomoto, R. Ando, H. Morita, and H. Nakayama, “Thermal Oxidation Rate of a Si3N4 Film and Its Masking Effect against Oxidation of Silicon,” Jpn. J. Appl. Phys. 17(6), 1049–1058 (1978).
[CrossRef]

Opt. Lett. (1)

Proc. IEEE (1)

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, W. Shih-Yuan, and R. S. Williams, “Nanoelectronic and Nanophotonic Interconnect,” Proc. IEEE 96(2), 230–247 (2008).
[CrossRef]

Solid-State Electron. (1)

C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Electron. 48(6), 961–967 (2004).
[CrossRef]

Other (6)

J. M. Fedeli, M. Migette, L. Cioccio, L. El Melhaoui, R. Orobtchouk, C. Seassal, P. Rojo-Romeo, F. Mandorlo, D. Marris-Morini, and L. Vivien, “Incorporation of a Photonic Layer at the Metallizations Levels of a CMOS Circuit,” in Group IV Photonics, 2006. 3rd IEEE International Conference on(2006), pp. 200–202.

F. Y. Gardes, G. T. Reed, A. P. Knights, G. Mashanovich, P. E. Jessop, L. Rowe, S. McFaul, D. Bruce, and N. G. Tarr, “Sub-micron optical waveguides for silicon photonics formed via the local oxidation of silicon (LOCOS),” in Silicon Photonics III(SPIE, San Jose, CA, USA, 2008), pp. 68980R–68984.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” (IEEE Computer Society Press, 2009), pp. 8–21.

C. W. Holzwarth, J. S. Orcutt, L. Hanqing, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes,” in Lasers and Electro-Optics, 2008 and 2008 Conference on Quantum Electronics and Laser Science. CLEO/QELS 2008.(2008), pp. 1–2.

D. Andriukaitis, and R. Anilionis, “Thermal Oxidation in LOCOS, PBL, and SWAMI Micro and nano Structures,” (2007), p. 75.

A. Shacham, K. Bergman, and L. P. Carloni, “On the Design of a Photonic Network-on-Chip,” in Networks-on-Chip(2007), pp. 53–64.

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Figures (4)

Fig. 1
Fig. 1

Simulated effects of wet oxidation on waveguide structure: (a) post over-etching and prior to oxidation, (b) 1 hour of oxidation, (c) 6 hours of oxidation, (d) 9 hours of oxidation.

Fig. 2
Fig. 2

Process flow: (a) bulk silicon wafer, (b) Si3N4 deposition, (c) lithographic waveguide definition, (d) ICP etch, (e) Si3N4 deposition, (f) ICP cap etch, (g) extended etch for quicker oxidation, (h) wet oxidation for buffer layer growth, (i) extended wet oxidation for waveguide underlayer flattening, (j) upper layer oxide deposition to complete optical buffer.

Fig. 3
Fig. 3

Final experimental waveguide shape shown: (a) closeup false color SEM of waveguide cross-section; (b) fundamental TE mode with effective index of 2.63, TM shown for comparison; (c) SEM showing buried oxide layer.

Fig. 4
Fig. 4

Experimental loss for varying lengths of waveguide measured at 1550 nm, and loss per length fit of 2.92 dB/cm.

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