Abstract

In order to achieve high-speed transmission over optical transport networks (OTNs) and maximize its throughput, we propose using a rate-adaptive polarization-multiplexed coded multilevel modulation with coherent detection based on component non-binary quasi-cyclic (QC) LDPC codes. Compared to prior-art bit-interleaved LDPC-coded modulation (BI-LDPC-CM) scheme, the proposed non-binary LDPC-coded modulation (NB-LDPC-CM) scheme not only reduces latency due to symbol- instead of bit-level processing but also provides either impressive reduction in computational complexity or striking improvements in coding gain depending on the constellation size. As the paper presents, compared to its prior-art binary counterpart, the proposed NB-LDPC-CM scheme addresses the needs of future OTNs, which are achieving the target BER performance and providing maximum possible throughput both over the entire lifetime of the OTN, better.

© 2010 OSA

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    [CrossRef]

2008

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[CrossRef]

2007

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[CrossRef]

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

2006

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[CrossRef]

I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006).
[CrossRef]

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

2005

H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005).
[CrossRef]

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[CrossRef]

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

2003

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[CrossRef]

1969

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[CrossRef]

1962

R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962).
[CrossRef]

Abdel-Ghaffar, K.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Anantharam, V.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[CrossRef]

Chen, C. L.

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[CrossRef]

Chen, J.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

Chen, L.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

Cvijetic, M.

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[CrossRef]

Dholakia, A.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

Djordjevic, I. B.

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[CrossRef]

I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006).
[CrossRef]

Eleftheriou, E.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

Fong, W.

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

Fossorier, M.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

Gallager, R. G.

R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962).
[CrossRef]

Hou, J.

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[CrossRef]

Hu, X.-Y.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

Huang, J.

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[CrossRef]

Lan, L.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Li, Z.-W.

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

Lin, S.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

Lui, H.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

Mansour, M. M.

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[CrossRef]

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[CrossRef]

Milstein, L. B.

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[CrossRef]

Nikolic, B.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[CrossRef]

Peterson, W. W.

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[CrossRef]

Shanbhag, N. R.

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[CrossRef]

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[CrossRef]

Shi, C.-J. R.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

Siegel, P. H.

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[CrossRef]

Tai, Y. Y.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Vasic, B.

I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006).
[CrossRef]

Wang, T.

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[CrossRef]

Weldon, E. J.

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[CrossRef]

Willett, P.

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[CrossRef]

Xu, L.

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[CrossRef]

Yang, L.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

Yeo, E.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[CrossRef]

Zeng, L.

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Zeng, L.-Q.

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

Zhang, T.

H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005).
[CrossRef]

Zhong, H.

H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005).
[CrossRef]

Zhou, S.

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[CrossRef]

IEEE Commun. Mag.

E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Commun. Mag. 41(8), 132–140 (2003).
[CrossRef]

IEEE J. Sel. Areas Comm.

J. Huang, S. Zhou, and P. Willett, “Nonbinary LDPC coding for multicarrier underwater acoustic communication,” IEEE J. Sel. Areas Comm. 26(9), 1684–1696 (2008).
[CrossRef]

IEEE J. Solid-state Circuits

M. M. Mansour, N. R. Shanbhag, M. M. Mansour, and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-state Circuits 41(3), 684–698 (2006).
[CrossRef]

IEEE Trans. Circ. Syst.

L. Yang, H. Lui, and C.-J. R. Shi, “Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder,” IEEE Trans. Circ. Syst. 53–4, 892–904 (2006).

IEEE Trans. Circuits Syst. I

H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits Syst. I 52(4), 766–775 (2005).
[CrossRef]

IEEE Trans. Commun.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun. 53(8), 1288–1299 (2005).
[CrossRef]

J. Hou, P. H. Siegel, and L. B. Milstein, “Design of multi-input multi-output systems based on low-density parity-check codes,” IEEE Trans. Commun. 53(4), 601–611 (2005).
[CrossRef]

Z.-W. Li, L. Chen, L.-Q. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity-check codes,” IEEE Trans. Commun. 54(1), 71–81 (2006).
[CrossRef]

IEEE Trans. Inf. Theory

L. Lan, L. Zeng, Y. Y. Tai, L. Chen, S. Lin, and K. Abdel-Ghaffar, “Construction of quasi-cyclic LDPC codes for AWGN and binary erasure channels: A finite field approach,” IEEE Trans. Inf. Theory 53(7), 2429–2458 (2007).
[CrossRef]

Inf. Control

C. L. Chen, W. W. Peterson, and E. J. Weldon., “Some results on quasi-cyclic codes,” Inf. Control 15(5), 407–423 (1969).
[CrossRef]

IRE Trans. Inf. Theory

R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory 8(1), 21–28 (1962).
[CrossRef]

J. Lightwave Technol.

I. B. Djordjevic and B. Vasic, “Multilevel coding in M-ary DPSK/differential QAM high-speed optical transmission with direct detection,” J. Lightwave Technol. 24(1), 420–428 (2006).
[CrossRef]

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Using LDPC-coded modulation and coherent detection for ultra high-speed optical transmission,” J. Lightwave Technol. 25(11), 3619–3625 (2007).
[CrossRef]

Other

R. D. Stieger, “Optical communication system with variable error correction coding,” Blakely, Sokolof, Taylor & Zafman LLP, US Patent Application Publication US 2003/0005385 A1, (2003).

A. Voicila, D. Declercq, F. Verdier, M. Fossorier, and P. Urard, “Low-complexity, low-memory EMS algorithm for non-binary LDPC codes,” in Proc. Int. Conf. on Commun., (Institute of Electrical and Electronics Engineers, Glasgow, Scotland, 2007), pp. 671–676.

R.-H. Peng, and R.-R. Chen, “Design of nonbinary LDPC codes over GF(q) for multiple-antenna transmission,” in Proc. Military Commun. Conf., (Institute of Electrical and Electronics Engineers, Washington, DC, 2006), pp. 1–7.

R.-H. Peng and R.-R. Chen, “Application of nonbinary LDPC cycle codes to MIMO channels,” IEEE Trans. Wireless Commun. 7–6, 2020–2026 (2008).

I. B. Djordjevic, M. Cvijetic, L. Xu, and T. Wang, “Proposal for beyond 100 Gb/s optical transmission based on bit-interleaved LDPC-coded modulation,” IEEE Photon. Technol. Lett. 19–12, 874–876 (2007).

M. Arabaci, I. B. Djordjevic, R. Saunders, and R. M. Marcoccia, “Rate-Adaptive Non-binary-LDPC-Coded Polarization-Multiplexed Multilevel Modulation with Coherent Detection for Optically-Routed Networks,” in Proc. Int. Conf. on Transparent Optical Networks (ICTON), (Institute of Electrical and Electronics Engineers, Azores, Portugal, 2009), Paper no. Tu.B2.2.

A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity check code decoder,” IEEE J. Solid-State Circuits 37–3, 404–412 (2002).

Z. Wang and Z. Cui, “Low-complexity high-speed decoder design for quasi-cyclic LDPC codes,” IEEE Trans. on Very Large Scale Integ. (VLSI) Syst. 15–1, 104 −114 (2007).

C. P. Fewer, M. F. Flanagan and A. D. Fagan “A versatile variable rate LDPC codec architecture,” IEEE Trans. Circuits Syst. I 54–10, 2240–2251 (2007).

A. J. de Lind Van Wijngaarden, R. C. Giles, S. K. Korotky, and X. Liu, “Rate-adaptive forward error correction for optical transport systems,” Lucent Technologies, Inc., US Patent Application Publication US 2009/0044079 A1, (2009).

O. Grestel, L. Paraschis, and P. Lothberg, “Variable forward error correction for optical communication links,” Cisco Technology, Inc., US Patent Application Publication US 2008/0256421 A1, (2008).

S. Lin, and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications (Prentice Hall, 2004).

M. C. Davey, Error-Correction using Low-Density Parity-Check Codes, Ph.D. dissertation, (University of Cambridge, 1999).

D. Declercq and M. Fossorier, “Decoding algorithms for nonbinary LDPC codes over GF(q),” IEEE Trans. Commun. 55–4, 633–643 (2007).

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Figures (5)

Fig. 1
Fig. 1

(a) Transmitter and (b) receiver configurations for the BI-LDPC-CM scheme.

Fig. 2
Fig. 2

(a) Transmitter and (b) receiver configurations for the NB-LDPC-CM scheme.

Fig. 3
Fig. 3

Operations performed at check nodes during MD-FFT-QSPA-based decoding.

Fig. 4
Fig. 4

BER performance curves for polarization-multiplexed systems employing BI-LDPC-CM with component codes at various code rates. Note that symbol rate Rs = 25 GS/s.

Fig. 5
Fig. 5

BER performance curves for polarization-multiplexed systems employing NB-LDPC-CM with component codes at various code rates. Note that symbol rate Rs = 25 GS/s.

Tables (2)

Tables Icon

Table 1 Parameters of Component NB-QC-LDPC Codes

Tables Icon

Table 2 Coding Gains (in dB) of NB-LDPC-CM Scheme with Component Codes at Various Code Rates

Equations (5)

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λ ( s ) = ln P ( s | r ) P ( s 0 | r ) = ln P ( r | s ) P ( s ) P ( r | s 0 ) P ( s 0 ) ,
H = [ H 0 , 0 H 0 , 1 H 0 , ρ 1 H 1 , 0 H 1 , 1 H 1 , ρ 1 H γ 1 , 0 H γ 1 , 1 H γ 1 , ρ 1 ] ,
15 m M b ( ρ 2 )
2 ρ q M ( m + 1 1 ( 2 ρ ) ) .
CR = 2 ρ q M ( m + 1 1 ( 2 ρ ) ) 15 m M b ( ρ 2 ) = 19 375 2 m ( m + 1 1 48 ) m 19 375 2 m ( m + 1 ) m .

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