Abstract

We demonstrate spectral tunability for microphotonic add-drop filters manufactured as ring resonators in a commercial 130 nm SOI CMOS technology. The filters are provisioned with integrated heaters built in CMOS for thermal tuning. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint using a bulk silicon micromachining process. An overall ~20x increase in the tuning efficiency has been demonstrated with a 100 µm radius ring as compared to a pre-micromachined device. A total of 3.9 mW of applied tuning power shifts the filter resonant peak across one free spectral node of the device. The Q-factor of the resonator remains unchanged after the co-integration process and hence this device geometry proves to be fully CMOS compatible. Additionally, after the cointegration process our result of 2π shift with 3.9mW power is among the best tuning performances for this class of devices. Finally, we examine scaling the tuning efficiency versus device footprint to develop a different performance criterion for an easier comparison to evaluate thermal tuning. Our criterion is defined as the unit of power to shift the device resonance by a full 2π phase shift.

© 2010 OSA

Full Article  |  PDF Article

References

  • View by:
  • |
  • |
  • |

  1. A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
    [CrossRef]
  2. J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
    [CrossRef]
  3. R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
    [CrossRef]
  4. C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
    [CrossRef]
  5. A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
    [CrossRef]
  6. X. Zheng, P. Koka, H. Schwetman, J. Lexau, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Silicon photonic WDM point-to-point network for multi-chip processor interconnects”, Proceedings of the 5th International Conference on Group IV Photonics, FB7, 380–382 (2008).
  7. I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004).
    [CrossRef]
  8. F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
    [CrossRef]
  9. X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
    [CrossRef] [PubMed]
  10. M. H. Khan, H. Shen, Y. Xuan, S. Xiao, and M. Qi, “Eight-Channel Microring Resonator Array with Accurately Controlled Channel Spacing”, CLEO/QELS (2008).
  11. M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic resonant microrings (ARMs) with directly integrated thermal microphotonics”, 2009 Conference on Lasers and Electro-Optics CLEO/QELS, CPDB10 (2009).
  12. I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010).
    [CrossRef]
  13. S. Sridaran and S. A. Bhave, “Nanophotonic devices on thin buried oxide Silicon-On-Insulator substrates,” Opt. Express 18(4), 3850–3857 (2010).
    [CrossRef] [PubMed]
  14. P. Sun and R. M. Reano, “Submilliwatt thermo-optic switches using free-standing silicon-on-insulator strip waveguides,” Opt. Express 18(8), 8406–8411 (2010).
    [CrossRef] [PubMed]
  15. J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kaertner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CTuBB3 (2008).
  16. C. Holzwarth, J. Orcutt, H. Li, M. Popovic, V. Stojanovic, J. Hoyt, R. Ram, and H. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CThKK5 (2009).
  17. N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
    [CrossRef]
  18. http://www.brewerscience.com/products/protek/wet-etch-protective-coating/

2010 (5)

2009 (1)

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

2007 (2)

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

2006 (2)

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

2004 (1)

I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004).
[CrossRef]

1997 (1)

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Abdalla, S.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Analui, B.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Asghari, M.

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

Baets, R.

I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004).
[CrossRef]

Balmater, E.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Barwicz, T.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Bhave, S. A.

Christiaens, I.

I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004).
[CrossRef]

Costa, J.

Cunningham, J. E.

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Dahlem, M. S.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Feng, D.

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

Gaitan, M.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Gan, F.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Geist, J.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Gloeckner, S.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Guckenberger, D.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Gunn, C.

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

Harrison, M.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Ho, R.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Holzwarth, C. W.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Ippen, E. P.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Kärtner, F. X.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Koka, P.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Koumans, R.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Krishnamoorthy, A. V.

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Kucharski, D.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Lexau, J.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Li, G.

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Liang, L.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Luo, Y.

Mekis, A.

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Milanovic, V.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Mirsaidi, S.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Mitchell, J. G.

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

Narasimha, A.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Pinguet, T.

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Popovic, M. A.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Raj, K.

Rakich, P. T.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Reano, R. M.

Schwetman, H.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Shubin, I.

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Sleboda, T.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Smith, H. I.

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Song, D.

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

Soref, R.

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

Sridaran, S.

Suehle, J. S.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Sun, P.

Tea, N. H.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Thacker, H.

Van Thourhout, D.

I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004).
[CrossRef]

Yao, J.

Zaghloul, M. E.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Zheng, X.

X. Zheng, I. Shubin, G. Li, T. Pinguet, A. Mekis, J. Yao, H. Thacker, Y. Luo, J. Costa, K. Raj, J. E. Cunningham, and A. V. Krishnamoorthy, “A tunable 1x4 silicon CMOS photonic wavelength multiplexer/demultiplexer for dense optical interconnects,” Opt. Express 18(5), 5151–5160 (2010).
[CrossRef] [PubMed]

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Zincke, C.

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

IEEE Photon. Switching (1)

F. Gan, T. Barwicz, M. A. Popović, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kärtner, “Maximizing the Thermo-Optic Tuning Range of Silicon Photonic Structures,” IEEE Photon. Switching 67–68 (2007).
[CrossRef]

Electron. Lett. (1)

I. Christiaens, D. Van Thourhout, and R. Baets, “Low-power thermo-optic tuning of vertically coupled microring resonators,” Electron. Lett. 40(9), 560–561 (2004).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron. (1)

R. Soref, “The past, present, and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

IEEE J. Solid-state Circuits (1)

A. Narasimha, B. Analui, L. Liang, T. Sleboda, S. Abdalla, E. Balmater, S. Gloeckner, D. Guckenberger, M. Harrison, R. Koumans, D. Kucharski, A. Mekis, S. Mirsaidi, D. Song, and T. Pinguet, “A Fully Integrated 4 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 μm CMOS SOI Technology,” IEEE J. Solid-state Circuits 42(12), 2736–2744 (2007).
[CrossRef]

IEEE Micro (1)

C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26(2), 58–66 (2006).
[CrossRef]

IEEE Trans. Adv. Packag. (1)

J. E. Cunningham, A. V. Krishnamoorthy, I. Shubin, X. Zheng, M. Asghari, D. Feng, and J. G. Mitchell, “Aligning Chips Face-to-Face for Dense Capacitive and Optical Communication,” IEEE Trans. Adv. Packag. 33(2), 389–397 (2010).
[CrossRef]

J. Microelectromech. Syst. (1)

N. H. Tea, V. Milanovic, C. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist, “Hybrid Postprocessing Etching for CMOS-Compatible MEMS,” J. Microelectromech. Syst. 6(4), 363–372 (1997).
[CrossRef]

Opt. Express (3)

Proc. IEEE (1)

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Proc. SPIE (1)

I. Shubin, “X. Zheng, H. Thacker, J. Yao, J. Costa, Y. Luo, G. Li, A. V. Krishnamoorthy, J.E. Cunningham, T. Pinguet, A. Mekis, “Thermally tunable SOI CMOS photonics circuits,” Proc. SPIE 7607, 76070C (2010).
[CrossRef]

Other (6)

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kaertner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CTuBB3 (2008).

C. Holzwarth, J. Orcutt, H. Li, M. Popovic, V. Stojanovic, J. Hoyt, R. Ram, and H. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” 2008 Conference on Lasers and Electro-Optics CLEO/QELS, CThKK5 (2009).

http://www.brewerscience.com/products/protek/wet-etch-protective-coating/

X. Zheng, P. Koka, H. Schwetman, J. Lexau, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Silicon photonic WDM point-to-point network for multi-chip processor interconnects”, Proceedings of the 5th International Conference on Group IV Photonics, FB7, 380–382 (2008).

M. H. Khan, H. Shen, Y. Xuan, S. Xiao, and M. Qi, “Eight-Channel Microring Resonator Array with Accurately Controlled Channel Spacing”, CLEO/QELS (2008).

M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic resonant microrings (ARMs) with directly integrated thermal microphotonics”, 2009 Conference on Lasers and Electro-Optics CLEO/QELS, CPDB10 (2009).

Cited By

OSA participates in CrossRef's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.

Alert me when this article is cited.


Figures (6)

Fig. 1
Fig. 1

Thermally tunable resonant waveguide structures: (a) schematic cross-section, (b) SEM image of the silicon waveguide ring with 24 µm diameter and its bus waveguides without the metal interconnects and interlayer dielectrics.

Fig. 2
Fig. 2

A fragment of the MUX/DEMUX circuit with two thermally tunable rings and their respective waveguide ports.

Fig. 3
Fig. 3

Filter transmission versus wavelength as a function of applied power to a ring MUX of 200 µm diameter.

Fig. 4
Fig. 4

A linear dependence of wavelength shift with applied electrical tuning power shown for different diameter rings.

Fig. 5
Fig. 5

Silicon photonic resonant structures with a substrate undercut. Top view (a) showing the heating elements and undercut area, and a respective cross-section (b) displaying the front and back side masking layers.

Fig. 6
Fig. 6

Thermal tuning of the ring with a 100 µm radius.

Metrics