Abstract

Conventional architectures for the implementation of Boolean logic are based on a network of bistable elements assembled to realize cascades of simple Boolean logic gates. Since each such gate has two input signals and only one output signal, such architectures are fundamentally dissipative in information and energy. Their serial nature also induces a latency in the processing time. In this paper we present a new, principally non-dissipative digital logic architecture which mitigates the above impediments. Unlike traditional computing architectures, the proposed architecture involves a distributed and parallel input scheme where logical functions are evaluated at the speed of light. The system is based on digital logic vectors rather than the Boolean scalars of electronic logic. The architecture employs a novel conception of cascading which utilizes the strengths of both optics and electronics while avoiding their weaknesses. It is inherently non-dissipative, respects the linear nature of interactions in pure optics, and harnesses the control advantages of electrons without reducing the speed advantages of optics. This new logic paradigm was specially developed with optical implementation in mind. However, it is suitable for other implementations as well, including conventional electronic devices.

© 2007 Optical Society of America

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  1. L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
    [CrossRef]
  2. A. B. VanderLugt, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-10, 139-145 (1964).
  3. H. J. Caulfield and J. Shamir, "Wave-particle duality processors - characteristics, requirements and applications," J. Opt. Soc. Am. A 7, 1314-1323 (1990).
    [CrossRef]
  4. J. Shamir, H. J. Caulfield, W. Micelli, and R. J. Seymour, "Optical Computing and the Fredkin Gates," Appl. Opt. 25, 1604-1607 (1986).
    [CrossRef]
  5. J. Shamir, "Three-dimensional optical interconnection gate array," Appl. Opt. 26, 3455-3457 (1987).
    [CrossRef] [PubMed]
  6. M. M. Mirsalehi, J. Shamir, and H. J. Caulfield, "Residue arithmetic processing utilizing optical Fredkin gate arrays," Appl. Opt. 26, 3940-3946 (1987).
    [CrossRef] [PubMed]
  7. K. M. Johnson, M. Surette, and J. Shamir, "Optical interconnection network using polarization-based ferroelectric liquid crystal gates," Appl. Opt. 27, 1727-1733 (1988).
    [CrossRef] [PubMed]
  8. E. Fredkin and T. Toffoli, "Conservative Logic," Int. J. Theor. Phys. 21, 219-253 (1982).
    [CrossRef]
  9. H. J. Caulfied, R. A. Soref, L. Qian, A. Zavalin, and J. Hardy, "Generalized Optical Logic Elements - GOLEs," under review.
  10. R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev. 5, 183-191 (1961).
    [CrossRef]
  11. S. Younis, "Asymptotically zero energy computing using split-level charge recovery logic," Ph.D. thesis, MIT (1994).
  12. S. Younis and T. Knight, "Asymptotically zero energy split-level charge recovery logic," in Proc. of 1994 International Workshop on Low Power Design, pp. 177-182 (1994).
  13. M. P. Frank, "Physical limits of computing. Lecture #24 Adiabatic CMOS," (2002). URL http://www.cise.ufl.edu/mpf/physlim/PhysLimL24.ppt.
  14. A. I. Zavalin, J. Shamir, C. S. Vikram, and H. J. Caulfield, "Achieving stabilization in interferometric logic operations," Appl. Opt. 45(2), 360-365 (2006).
    [CrossRef]
  15. H. J. Caulfied and R. A. Soref, "Universal reconfigurable optical logic with silicon-on-insulator resonant structures," Photonics Nanostruct. Fundam. Appl. (to appear).

2006

1990

1988

1987

J. Shamir, "Three-dimensional optical interconnection gate array," Appl. Opt. 26, 3455-3457 (1987).
[CrossRef] [PubMed]

M. M. Mirsalehi, J. Shamir, and H. J. Caulfield, "Residue arithmetic processing utilizing optical Fredkin gate arrays," Appl. Opt. 26, 3940-3946 (1987).
[CrossRef] [PubMed]

1986

1982

E. Fredkin and T. Toffoli, "Conservative Logic," Int. J. Theor. Phys. 21, 219-253 (1982).
[CrossRef]

1964

A. B. VanderLugt, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-10, 139-145 (1964).

1961

R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev. 5, 183-191 (1961).
[CrossRef]

1960

L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
[CrossRef]

Caulfield, H. J.

Cutrona, L. J.

L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
[CrossRef]

Fredkin, E.

E. Fredkin and T. Toffoli, "Conservative Logic," Int. J. Theor. Phys. 21, 219-253 (1982).
[CrossRef]

Johnson, K. M.

Landauer, R.

R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev. 5, 183-191 (1961).
[CrossRef]

Leith, E. N.

L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
[CrossRef]

Micelli, W.

Mirsalehi, M. M.

M. M. Mirsalehi, J. Shamir, and H. J. Caulfield, "Residue arithmetic processing utilizing optical Fredkin gate arrays," Appl. Opt. 26, 3940-3946 (1987).
[CrossRef] [PubMed]

Palermo, C. J.

L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
[CrossRef]

Porcello, L. J.

L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
[CrossRef]

Seymour, R. J.

Shamir, J.

Surette, M.

Toffoli, T.

E. Fredkin and T. Toffoli, "Conservative Logic," Int. J. Theor. Phys. 21, 219-253 (1982).
[CrossRef]

VanderLugt, A. B.

A. B. VanderLugt, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-10, 139-145 (1964).

Vikram, C. S.

Zavalin, A. I.

Appl. Opt.

IBM J. Res. Dev.

R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev. 5, 183-191 (1961).
[CrossRef]

Int. J. Theor. Phys.

E. Fredkin and T. Toffoli, "Conservative Logic," Int. J. Theor. Phys. 21, 219-253 (1982).
[CrossRef]

IRE Trans. Inf. Theory

L. J. Cutrona, E. N. Leith, C. J. Palermo, and L. J. Porcello, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-6, 386-400 (1960).
[CrossRef]

A. B. VanderLugt, "Optical data processing and filtering systems," IRE Trans. Inf. Theory IT-10, 139-145 (1964).

J. Opt. Soc. Am. A

Other

H. J. Caulfied and R. A. Soref, "Universal reconfigurable optical logic with silicon-on-insulator resonant structures," Photonics Nanostruct. Fundam. Appl. (to appear).

H. J. Caulfied, R. A. Soref, L. Qian, A. Zavalin, and J. Hardy, "Generalized Optical Logic Elements - GOLEs," under review.

S. Younis, "Asymptotically zero energy computing using split-level charge recovery logic," Ph.D. thesis, MIT (1994).

S. Younis and T. Knight, "Asymptotically zero energy split-level charge recovery logic," in Proc. of 1994 International Workshop on Low Power Design, pp. 177-182 (1994).

M. P. Frank, "Physical limits of computing. Lecture #24 Adiabatic CMOS," (2002). URL http://www.cise.ufl.edu/mpf/physlim/PhysLimL24.ppt.

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Figures (10)

Fig. 1.
Fig. 1.

XOR/XNOR computed with a series of directed logic elements

Fig. 2.
Fig. 2.

OR/NOR circuit in directed logic

Fig. 3.
Fig. 3.

Recursive cascading to produce a complex circuit: OR circuits are nested within an AND circuit as indicated by the arrows.

Fig. 4.
Fig. 4.

The final circuit for (A OR B) AND C

Fig. 5.
Fig. 5.

A simpler circuit computing the same function as Figure 4

Fig. 6.
Fig. 6.

AND/NAND circuit

Fig. 7.
Fig. 7.

Circuit for IF A, THEN B and its negation A AND NOT B

Fig. 8.
Fig. 8.

Circuit for IF B, THEN A and its negation B AND NOT A

Fig. 9.
Fig. 9.

OR/NOR circuit

Fig. 10.
Fig. 10.

A fully cascadeable XOR/XNOR circuit.The XOR gate shown in Figure 1 works only for XOR among literals, it can’t be cascaded into in the style of section 2.2. The XOR design shown here is fully cascadeable though somewhat larger.

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