Abstract

Complex photonic-integrated circuits (PIC) may have strongly non-planar topologies that require waveguide crossings (WGX) when realized in single-layer integration platforms. The number of WGX increases rapidly with the complexity of the circuit, in particular when it comes to highly interconnected optical switch topologies. Here, we present a concept for WGX-free PIC that relies on 3D-printed freeform waveguide overpasses (WOP). We experimentally demonstrate the viability of our approach using the example of a 4 × 4 switch-and-select (SAS) circuit realized on the silicon photonic platform. We further present a comprehensive graph-theoretical analysis of different n × n SAS circuit topologies. We find that for increasing port counts n of the SAS circuit, the number of WGX increases with n4, whereas the number of WOP increases only in proportion to n2.

© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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2019 (1)

2018 (2)

W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
[Crossref]

M. R. Billah, M. Blaicher, T. Hoose, P.-I. Dietrich, P. Marin-Palomo, N. Lindenmann, A. Nesic, A. Hofmann, U. Troppenz, M. Moehrle, S. Randel, W. Freude, and C. Koos, “Hybrid integration of silicon photonics circuits and InP lasers by photonic wire bonding,” Optica 5(7), 876–883 (2018).
[Crossref]

2017 (3)

2016 (2)

K. Itoh, Y. Kuno, Y. Hayashi, J. Suzuki, N. Hojo, T. Amemiya, N. Nishiyama, and S. Arai, “Crystalline/amorphous Si integrated optical couplers for 2D/3D interconnection,” IEEE J. Sel. Top. Quantum Electron. 22(6), 255–263 (2016).
[Crossref]

T. J. Seok, N. Quack, S. Han, R. S. Muller, and M. C. Wu, “Large-scale broadband digital silicon photonic switches with vertical adiabatic couplers,” Optica 3(1), 64–70 (2016).
[Crossref]

2015 (5)

2014 (1)

2013 (5)

2012 (3)

2010 (1)

F. Chang, K. Onohara, and T. Mizuochi, “Forward error correction for 100 G transport networks,” IEEE Commun. Mag. 48(3), S48–S55 (2010).
[Crossref]

2009 (1)

2006 (1)

E. de Klerk, J. Maharry, D. V. Pasechnik, R. B. Richter, and G. Salazar, “Improved bounds for the crossing numbers of Km,n and Kn,” SIAM J. Discrete Math. 20(1), 189–202 (2006).
[Crossref]

2004 (1)

M. Deubel, G. von Freymann, M. Wegener, S. Pereira, K. Busch, and C. M. Soukoulis, “Direct laser writing of three-dimensional photonic-crystal templates for telecommunications,” Nat. Mater. 3(7), 444–447 (2004).
[Crossref]

2003 (1)

A. Riskin, “On the outerplanar crossing numbers of Km,n,” Bull. Inst. Combin. Appl. 39, 16–20 (2003).

1983 (1)

M. R. Garey and D. S. Johnson, “Crossing number is NP-complete,” SIAM J. Alg. Disc. Meth. 4(3), 312–316 (1983).
[Crossref]

1955 (1)

C. Zarankiewicz, “On a problem of P. Turan concerning graphs,” Fundam. Math. 41(1), 137–145 (1955).
[Crossref]

1930 (1)

C. Kuratowski, “Sur le problème des courbes gauches en Topologie,” Fundam. Math. 15(1), 271–283 (1930).
[Crossref]

1923 (1)

A. Errera, “Un théorème sur les liaisons,” C. R. Acad. Sci. Paris 177, 489–491 (1923).

Abbaslou, S.

W. Song, R. Gatdula, S. Abbaslou, M. Lu, A. Stein, W. Y.-C. Lai, J. Provine, R. F. W. Pease, D. N. Christodoulides, and W. Jiang, “High-density waveguide superlattices with low crosstalk,” Nat. Commun. 6(1), 7027 (2015).
[Crossref]

Abrams, N. C.

Q. Cheng, L. Y. Dai, M. Bahadori, N. C. Abrams, P. E. Morrissey, M. Glick, P. O’Brien, and K. Bergman, “Si/SiN microring-based optical router in switch-and-select topology,” in 44th European Conference on Optical Communications (ECOC) (IEEE, 2018), pp. 1–3.

Alloatti, L.

J. Pfeifle, L. Alloatti, W. Freude, J. Leuthold, and C. Koos, “Silicon-organic hybrid phase shifter based on a slot waveguide with a liquid-crystal cladding,” Opt. Express 20(14), 15359–15376 (2012).
[Crossref]

L. Alloatti, D. Korn, J. Pfeifle, R. Palmer, S. Koeber, M. Baier, R. Schmogrow, S. Diebold, P. Pahl, T. Zwick, H. Yu, W. Bogaerts, R. Baets, M. Fournier, J. Fedeli, R. Dinu, C. Koos, W. Freude, and J. Leuthold, “Silicon-organic hybrid devices,” Proc. SPIE 8629, 86290P (2013).

Amemiya, T.

K. Itoh, Y. Kuno, Y. Hayashi, J. Suzuki, N. Hojo, T. Amemiya, N. Nishiyama, and S. Arai, “Crystalline/amorphous Si integrated optical couplers for 2D/3D interconnection,” IEEE J. Sel. Top. Quantum Electron. 22(6), 255–263 (2016).
[Crossref]

Arai, S.

K. Itoh, Y. Kuno, Y. Hayashi, J. Suzuki, N. Hojo, T. Amemiya, N. Nishiyama, and S. Arai, “Crystalline/amorphous Si integrated optical couplers for 2D/3D interconnection,” IEEE J. Sel. Top. Quantum Electron. 22(6), 255–263 (2016).
[Crossref]

Baehr-Jones, T.

M. Hochberg, N. C. Harris, R. Ding, Y. Zhang, A. Novack, Z. Xuan, and T. Baehr-Jones, “Silicon photonics: The next fabless semiconductor industry,” IEEE Solid-State Circuits Mag. 5(1), 48–58 (2013).
[Crossref]

Y. Ma, Y. Zhang, S. Yang, A. Novack, R. Ding, A. E.-J. Lim, G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect,” Opt. Express 21(24), 29374–29382 (2013).
[Crossref]

C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

Baets, R.

L. Alloatti, D. Korn, J. Pfeifle, R. Palmer, S. Koeber, M. Baier, R. Schmogrow, S. Diebold, P. Pahl, T. Zwick, H. Yu, W. Bogaerts, R. Baets, M. Fournier, J. Fedeli, R. Dinu, C. Koos, W. Freude, and J. Leuthold, “Silicon-organic hybrid devices,” Proc. SPIE 8629, 86290P (2013).

Bahadori, M.

Q. Cheng, L. Y. Dai, M. Bahadori, N. C. Abrams, P. E. Morrissey, M. Glick, P. O’Brien, and K. Bergman, “Si/SiN microring-based optical router in switch-and-select topology,” in 44th European Conference on Optical Communications (ECOC) (IEEE, 2018), pp. 1–3.

Baier, M.

L. Alloatti, D. Korn, J. Pfeifle, R. Palmer, S. Koeber, M. Baier, R. Schmogrow, S. Diebold, P. Pahl, T. Zwick, H. Yu, W. Bogaerts, R. Baets, M. Fournier, J. Fedeli, R. Dinu, C. Koos, W. Freude, and J. Leuthold, “Silicon-organic hybrid devices,” Proc. SPIE 8629, 86290P (2013).

Balthasar, G.

Bergman, K.

Q. Cheng, L. Y. Dai, M. Bahadori, N. C. Abrams, P. E. Morrissey, M. Glick, P. O’Brien, and K. Bergman, “Si/SiN microring-based optical router in switch-and-select topology,” in 44th European Conference on Optical Communications (ECOC) (IEEE, 2018), pp. 1–3.

Bergmen, K.

C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

Bernier, E.

W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
[Crossref]

W. D. Sacher, J. C. Mikkelsen, P. Dumais, J. Jiang, D. Goodwill, X. Luo, Y. Huang, Y. Yang, A. Bois, P. G.-Q. Lo, E. Bernier, and J. K. S. Poon, “Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and interlayer transitions,” Opt. Express 25(25), 30862–30875 (2017).
[Crossref]

Billah, M.

T. Hoose, M. Billah, M. Blaicher, P. Marin, P.-I. Dietrich, A. Hofmann, U. Troppenz, M. Moehrle, N. Lindenmann, M. Thiel, P. Simon, J. Hoffmann, M. L. Goedecke, W. Freude, and C. Koos, “Multi-Chip integration by photonic wire bonding: connecting surface and edge emitting lasers to silicon chips,” in Optical Fiber Communications Conference and Exhibition (OFC) (IEEE, 2016), pp. 1–3.

Billah, M. R.

Blaicher, M.

M. R. Billah, M. Blaicher, T. Hoose, P.-I. Dietrich, P. Marin-Palomo, N. Lindenmann, A. Nesic, A. Hofmann, U. Troppenz, M. Moehrle, S. Randel, W. Freude, and C. Koos, “Hybrid integration of silicon photonics circuits and InP lasers by photonic wire bonding,” Optica 5(7), 876–883 (2018).
[Crossref]

M. Blaicher, M. R. Billah, T. Hoose, P.-I. Dietrich, A. Hofmann, S. Randel, W. Freude, and C. Koos, “3D-Printed ultra-broadband highly efficient out-of-plane coupler for photonic integrated circuits,” in Conference on Lasers and Electro-Optics (CLEO) (Optical Society of America, 2018), paper STh1A.1.

T. Hoose, M. Billah, M. Blaicher, P. Marin, P.-I. Dietrich, A. Hofmann, U. Troppenz, M. Moehrle, N. Lindenmann, M. Thiel, P. Simon, J. Hoffmann, M. L. Goedecke, W. Freude, and C. Koos, “Multi-Chip integration by photonic wire bonding: connecting surface and edge emitting lasers to silicon chips,” in Optical Fiber Communications Conference and Exhibition (OFC) (IEEE, 2016), pp. 1–3.

A. Nesic, M. Blaicher, T. Hoose, M. Lauermann, Y. Kutuvantavida, W. Freude, and C. Koos, “Hybrid 2D/3D photonic integration for non-planar circuit topologies,” in 42nd European Conference on Optical Communications (ECOC) (IEEE, 2016), paper W.3.F.4.

Bogaerts, W.

L. Alloatti, D. Korn, J. Pfeifle, R. Palmer, S. Koeber, M. Baier, R. Schmogrow, S. Diebold, P. Pahl, T. Zwick, H. Yu, W. Bogaerts, R. Baets, M. Fournier, J. Fedeli, R. Dinu, C. Koos, W. Freude, and J. Leuthold, “Silicon-organic hybrid devices,” Proc. SPIE 8629, 86290P (2013).

Bois, A.

Buckley, S.

J. Chiles, S. Buckley, N. Nader, S. W. Nam, R. P. Mirin, and J. M. Shainline, “Multi-planar amorphous silicon photonics with compact interplanar couplers, cross talk mitigation, and low crossing loss,” APL Photonics 2(11), 116101 (2017).
[Crossref]

Busch, K.

M. Deubel, G. von Freymann, M. Wegener, S. Pereira, K. Busch, and C. M. Soukoulis, “Direct laser writing of three-dimensional photonic-crystal templates for telecommunications,” Nat. Mater. 3(7), 444–447 (2004).
[Crossref]

Chang, F.

F. Chang, K. Onohara, and T. Mizuochi, “Forward error correction for 100 G transport networks,” IEEE Commun. Mag. 48(3), S48–S55 (2010).
[Crossref]

Chen, L.

Chen, R. T.

Chen, Y. K.

Cheng, Q.

Q. Cheng, L. Y. Dai, M. Bahadori, N. C. Abrams, P. E. Morrissey, M. Glick, P. O’Brien, and K. Bergman, “Si/SiN microring-based optical router in switch-and-select topology,” in 44th European Conference on Optical Communications (ECOC) (IEEE, 2018), pp. 1–3.

Chiles, J.

J. Chiles, S. Buckley, N. Nader, S. W. Nam, R. P. Mirin, and J. M. Shainline, “Multi-planar amorphous silicon photonics with compact interplanar couplers, cross talk mitigation, and low crossing loss,” APL Photonics 2(11), 116101 (2017).
[Crossref]

Christodoulides, D. N.

W. Song, R. Gatdula, S. Abbaslou, M. Lu, A. Stein, W. Y.-C. Lai, J. Provine, R. F. W. Pease, D. N. Christodoulides, and W. Jiang, “High-density waveguide superlattices with low crosstalk,” Nat. Commun. 6(1), 7027 (2015).
[Crossref]

Chrostowski, L.

L. Chrostowski and M. Hochberg, Silicon Photonics Design (Cambridge University, 2015).

Dai, L. Y.

Q. Cheng, L. Y. Dai, M. Bahadori, N. C. Abrams, P. E. Morrissey, M. Glick, P. O’Brien, and K. Bergman, “Si/SiN microring-based optical router in switch-and-select topology,” in 44th European Conference on Optical Communications (ECOC) (IEEE, 2018), pp. 1–3.

de Klerk, E.

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C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

Li, S.

Li, T.

I. Kaminow, T. Li, and A. Willner, Optical Fiber Telecommunications, Volume VIB, 6th edition (Elsevier Science Publishing Company, Inc., 2013).

Li, Y.

W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
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Y. Ma, Y. Zhang, S. Yang, A. Novack, R. Ding, A. E.-J. Lim, G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect,” Opt. Express 21(24), 29374–29382 (2013).
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C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

Lindenmann, N.

Liu, G.

Liu, Y.

Y. Liu, J. M. Shainline, X. Zeng, and M. A. Popović, “Ultra-low-loss CMOS-compatible waveguide crossing arrays based on multimode Bloch waves and imaginary coupling,” Opt. Lett. 39(2), 335–338 (2014).
[Crossref]

C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

Lo, G.-Q.

Lo, P. G.-Q.

W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
[Crossref]

W. D. Sacher, J. C. Mikkelsen, P. Dumais, J. Jiang, D. Goodwill, X. Luo, Y. Huang, Y. Yang, A. Bois, P. G.-Q. Lo, E. Bernier, and J. K. S. Poon, “Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and interlayer transitions,” Opt. Express 25(25), 30862–30875 (2017).
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W. Song, R. Gatdula, S. Abbaslou, M. Lu, A. Stein, W. Y.-C. Lai, J. Provine, R. F. W. Pease, D. N. Christodoulides, and W. Jiang, “High-density waveguide superlattices with low crosstalk,” Nat. Commun. 6(1), 7027 (2015).
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W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
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W. D. Sacher, J. C. Mikkelsen, P. Dumais, J. Jiang, D. Goodwill, X. Luo, Y. Huang, Y. Yang, A. Bois, P. G.-Q. Lo, E. Bernier, and J. K. S. Poon, “Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and interlayer transitions,” Opt. Express 25(25), 30862–30875 (2017).
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Y. Ma, Y. Zhang, S. Yang, A. Novack, R. Ding, A. E.-J. Lim, G.-Q. Lo, T. Baehr-Jones, and M. Hochberg, “Ultralow loss single layer submicron silicon waveguide crossing for SOI optical interconnect,” Opt. Express 21(24), 29374–29382 (2013).
[Crossref]

C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

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E. de Klerk, J. Maharry, D. V. Pasechnik, R. B. Richter, and G. Salazar, “Improved bounds for the crossing numbers of Km,n and Kn,” SIAM J. Discrete Math. 20(1), 189–202 (2006).
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W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
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Marin-Palomo, P.

Matsuura, H.

K. Suzuki, R. Konoike, K. Tanizawa, S. Suda, H. Matsuura, K. Ikeda, S. Namiki, and H. Kawashima, “Ultralow-crosstalk and broadband multi-port optical switch using SiN/Si double-layer platform,” in Opto-Electronics and Communications Conference (OECC) and Photonics Global Conference (PGC) (IEEE, 2017), pp. 1–2.

Mikkelsen, J. C.

W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
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W. D. Sacher, J. C. Mikkelsen, P. Dumais, J. Jiang, D. Goodwill, X. Luo, Y. Huang, Y. Yang, A. Bois, P. G.-Q. Lo, E. Bernier, and J. K. S. Poon, “Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and interlayer transitions,” Opt. Express 25(25), 30862–30875 (2017).
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J. Chiles, S. Buckley, N. Nader, S. W. Nam, R. P. Mirin, and J. M. Shainline, “Multi-planar amorphous silicon photonics with compact interplanar couplers, cross talk mitigation, and low crossing loss,” APL Photonics 2(11), 116101 (2017).
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M. R. Billah, M. Blaicher, T. Hoose, P.-I. Dietrich, P. Marin-Palomo, N. Lindenmann, A. Nesic, A. Hofmann, U. Troppenz, M. Moehrle, S. Randel, W. Freude, and C. Koos, “Hybrid integration of silicon photonics circuits and InP lasers by photonic wire bonding,” Optica 5(7), 876–883 (2018).
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Morrissey, P. E.

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K. Suzuki, R. Konoike, K. Tanizawa, S. Suda, H. Matsuura, K. Ikeda, S. Namiki, and H. Kawashima, “Ultralow-crosstalk and broadband multi-port optical switch using SiN/Si double-layer platform,” in Opto-Electronics and Communications Conference (OECC) and Photonics Global Conference (PGC) (IEEE, 2017), pp. 1–2.

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Nesic, A.

M. R. Billah, M. Blaicher, T. Hoose, P.-I. Dietrich, P. Marin-Palomo, N. Lindenmann, A. Nesic, A. Hofmann, U. Troppenz, M. Moehrle, S. Randel, W. Freude, and C. Koos, “Hybrid integration of silicon photonics circuits and InP lasers by photonic wire bonding,” Optica 5(7), 876–883 (2018).
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K. Itoh, Y. Kuno, Y. Hayashi, J. Suzuki, N. Hojo, T. Amemiya, N. Nishiyama, and S. Arai, “Crystalline/amorphous Si integrated optical couplers for 2D/3D interconnection,” IEEE J. Sel. Top. Quantum Electron. 22(6), 255–263 (2016).
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Novack, A.

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M. Hochberg, N. C. Harris, R. Ding, Y. Zhang, A. Novack, Z. Xuan, and T. Baehr-Jones, “Silicon photonics: The next fabless semiconductor industry,” IEEE Solid-State Circuits Mag. 5(1), 48–58 (2013).
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C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

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Q. Cheng, L. Y. Dai, M. Bahadori, N. C. Abrams, P. E. Morrissey, M. Glick, P. O’Brien, and K. Bergman, “Si/SiN microring-based optical router in switch-and-select topology,” in 44th European Conference on Optical Communications (ECOC) (IEEE, 2018), pp. 1–3.

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Onohara, K.

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C. Galland, A. Novack, Y. Liu, R. Ding, M. Gould, T. Baehr-Jones, Q. Li, Y. Yang, Y. Ma, Y. Zhang, K. Padmaraju, K. Bergmen, A. E.-J. Lim, G.-Q. Lo, and M. Hochberg, “A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics,” Proc. SPIE 8767, 87670G (2013).

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L. Alloatti, D. Korn, J. Pfeifle, R. Palmer, S. Koeber, M. Baier, R. Schmogrow, S. Diebold, P. Pahl, T. Zwick, H. Yu, W. Bogaerts, R. Baets, M. Fournier, J. Fedeli, R. Dinu, C. Koos, W. Freude, and J. Leuthold, “Silicon-organic hybrid devices,” Proc. SPIE 8629, 86290P (2013).

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E. de Klerk, J. Maharry, D. V. Pasechnik, R. B. Richter, and G. Salazar, “Improved bounds for the crossing numbers of Km,n and Kn,” SIAM J. Discrete Math. 20(1), 189–202 (2006).
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Pease, R. F. W.

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Poon, J. K.

Poon, J. K. S.

W. D. Sacher, J. C. Mikkelsen, Y. Huang, J. C. C. Mak, Z. Yong, X. Luo, Y. Li, P. Dumais, J. Jiang, D. Goodwill, E. Bernier, P. G.-Q. Lo, and J. K. S. Poon, “Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-D photonic circuits and devices,” Proc. IEEE 106(12), 2232–2245 (2018).
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Provine, J.

W. Song, R. Gatdula, S. Abbaslou, M. Lu, A. Stein, W. Y.-C. Lai, J. Provine, R. F. W. Pease, D. N. Christodoulides, and W. Jiang, “High-density waveguide superlattices with low crosstalk,” Nat. Commun. 6(1), 7027 (2015).
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E. de Klerk, J. Maharry, D. V. Pasechnik, R. B. Richter, and G. Salazar, “Improved bounds for the crossing numbers of Km,n and Kn,” SIAM J. Discrete Math. 20(1), 189–202 (2006).
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E. de Klerk, J. Maharry, D. V. Pasechnik, R. B. Richter, and G. Salazar, “Improved bounds for the crossing numbers of Km,n and Kn,” SIAM J. Discrete Math. 20(1), 189–202 (2006).
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Seok, T. J.

Shainline, J. M.

J. Chiles, S. Buckley, N. Nader, S. W. Nam, R. P. Mirin, and J. M. Shainline, “Multi-planar amorphous silicon photonics with compact interplanar couplers, cross talk mitigation, and low crossing loss,” APL Photonics 2(11), 116101 (2017).
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Y. Liu, J. M. Shainline, X. Zeng, and M. A. Popović, “Ultra-low-loss CMOS-compatible waveguide crossing arrays based on multimode Bloch waves and imaginary coupling,” Opt. Lett. 39(2), 335–338 (2014).
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Simon, P.

T. Hoose, M. Billah, M. Blaicher, P. Marin, P.-I. Dietrich, A. Hofmann, U. Troppenz, M. Moehrle, N. Lindenmann, M. Thiel, P. Simon, J. Hoffmann, M. L. Goedecke, W. Freude, and C. Koos, “Multi-Chip integration by photonic wire bonding: connecting surface and edge emitting lasers to silicon chips,” in Optical Fiber Communications Conference and Exhibition (OFC) (IEEE, 2016), pp. 1–3.

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W. Song, R. Gatdula, S. Abbaslou, M. Lu, A. Stein, W. Y.-C. Lai, J. Provine, R. F. W. Pease, D. N. Christodoulides, and W. Jiang, “High-density waveguide superlattices with low crosstalk,” Nat. Commun. 6(1), 7027 (2015).
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Stein, A.

W. Song, R. Gatdula, S. Abbaslou, M. Lu, A. Stein, W. Y.-C. Lai, J. Provine, R. F. W. Pease, D. N. Christodoulides, and W. Jiang, “High-density waveguide superlattices with low crosstalk,” Nat. Commun. 6(1), 7027 (2015).
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T. Hoose, M. Billah, M. Blaicher, P. Marin, P.-I. Dietrich, A. Hofmann, U. Troppenz, M. Moehrle, N. Lindenmann, M. Thiel, P. Simon, J. Hoffmann, M. L. Goedecke, W. Freude, and C. Koos, “Multi-Chip integration by photonic wire bonding: connecting surface and edge emitting lasers to silicon chips,” in Optical Fiber Communications Conference and Exhibition (OFC) (IEEE, 2016), pp. 1–3.

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M. R. Billah, M. Blaicher, T. Hoose, P.-I. Dietrich, P. Marin-Palomo, N. Lindenmann, A. Nesic, A. Hofmann, U. Troppenz, M. Moehrle, S. Randel, W. Freude, and C. Koos, “Hybrid integration of silicon photonics circuits and InP lasers by photonic wire bonding,” Optica 5(7), 876–883 (2018).
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M. Deubel, G. von Freymann, M. Wegener, S. Pereira, K. Busch, and C. M. Soukoulis, “Direct laser writing of three-dimensional photonic-crystal templates for telecommunications,” Nat. Mater. 3(7), 444–447 (2004).
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J. Sun, E. Timurdogan, A. Yaacobi, E. S. Hosseini, and M. R. Watts, “Large-scale nanophotonic phased array,” Nature 493(7431), 195–199 (2013).
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Figures (8)

Fig. 1.
Fig. 1. Concept and implementation of waveguide overpasses (WOP) on the silicon photonic (SiP) platform. (a) The WOP is written into a liquid negative-tone photoresist that is deposited onto the PIC. For better coupling to the SiP on-chip waveguides, the SiO2 cladding is locally removed down to the buried oxide (BOX) layer. Inset (1): The spatial resolution of the two-photon lithography is determined by the size of the volumetric pixel (voxel) that results from two-photon polymerization. Inset (2): Tapers in the WOP and in the SiP waveguide improve the coupling efficiency. (b) Scanning electron microscope (SEM) image of the WOP (colors were added by image processing). (c)-(e) Close-ups of different parts of the WOP. Position markers indicate the positions of the SiP waveguide ends that need to be interconnected. During fabrication of our chip, the SiO2 cladding layer has been unintentionally over-etched, and part of the BOX has been unintentionally removed, see Subfigure (e).
Fig. 2.
Fig. 2. Comparison of layouts of a 4 × 4 optical switch-and-select (SAS) circuit for surface coupling. (a) Basic layout for single-layer waveguide technology without any optimization for reduced numbers of waveguide crossings (WGX). (b) Optimal layout for single-layer waveguide technology, minimizing the number of WGX by routing of waveguides around the coupling elements. The formula for $\eta _{n,n}^{\textrm{(surf)}}$ is a conjecture for the minimum possible number of WGX for an n × n SAS, if the 1 × n and n × 1 switches at the input and output ports are lumped elements (LE) [10,11]. For large port counts n, the number of WGX is conjectured to scale with n4/16. (c) Best found, but not necessarily optimal layout for a single-layer 4 × 4 SAS circuit, in which the 1 × 4 and 4 × 1 switches have been realized as binary trees (BT) of 1 × 2 and 2 × 1 switches. A general analysis of this circuit topology for arbitrary n is subject to ongoing investigations. (d) Best found, but not necessarily optimal WGX-free layout for hybrid 2D/3D circuits, minimizing the number of WOP. The switches are realized as BT in the same way as in (c). The formula for $\mu _{n,n}^{\textrm{(surf,}\ \textrm{BT)}}$ is an upper bound for the minimum number of WOP. The optical paths that were used for the crosstalk measurement in Section 4 are marked in green (Path 1) and in blue (Path 2). The arrows indicate the direction of light propagation for the crosstalk measurement. The drive current of MZI1 is modulated by a sinusoidal signal for highly sensitive lock-in detection of the weak crosstalk signals.
Fig. 3.
Fig. 3. Experimental demonstration of the 4 × 4 SAS with WOP. The layout of the SAS circuit is similar to the one depicted in Fig. 2(d). (a) Experimental setup. A multi-channel current source (CS) is used to drive different subsets of 16 out of the overall 24 optical 1 × 2 and 2 × 1 MZI switches via two multi-contact probe wedges (MCW). This allows testing of all 16 possible optical paths that connect the various input and output ports of the 4 × 4 SAS PIC. A tunable laser source (TLS) and a polarization controller (PC) are used to generate continuous-wave (CW) test signals that are launched to the various ports of the SAS PIC via a single-mode fiber (SMF) and grating couplers (GC). Each of the four optical outputs can be probed by another SMF, and the output signal is analyzed with an optical power meter (OPM) and an optical spectrum analyzer (OSA) that allows to perform a wavelength sweep that is synchronized with the TLS. (b) Microscope image of the SAS PIC with electrical and optical connections. (c) Microscope image of two waveguide overpasses (WOP), which bridge three and four SiP strip waveguides, respectively. A low-index cladding material is locally deposited with high precision to cover the printed WOP without blocking the nearby grating couplers. (d) Transmission spectra of various optical paths through the switch. Pale blue: Transmission spectra of 12 optical paths through the SAS PIC that do not contain any WOP (w/o WOP). Bright blue: Average transmission of the 12 paths w/o WOP. Pale red: Transmission spectra of two sets of two optical paths each, each set containing the same WOP (w/ WOP1; w/ WOP2). Bright red: Average transmission of each of the two sets w/ WOP. Black: Transmission spectra of WOP1 and WOP2.
Fig. 4.
Fig. 4. Different graph drawings of a surface-coupled 5 × 5 and 4 × 4 SAS circuit: (a) Graph drawing of a 5 × 5 SAS circuit where 1 × 5 and 5 × 1 switches at the input and output ports are realized as LE. The circuit is modeled by a complete bipartite graph K5,5, and the arrangement of vertices of sets M and N is such that the drawing results in the number of crossings equal to the conjectured crossing number given by Eq. (6). The two edges depicted in blue are the edges with the maximum number of crossings, which determine the local crossing number of this particular graph drawing, as given by Eq. (7). (b) Planar-edge-crossing-free graph representation of the same circuit. The edges depicted in blue represent a spanning maximum planar subgraph of K5,5. The remaining edges are realized with help of 3D edges (representing WOP) depicted as dashed red lines, which are routed outside the plane of the drawing and avoid crossings with the planar edges. Each 3D edge connects to a pair of planar edges depicted in black, that are linked to vertices at the respective other end. (c) If the 1 × 5 and 5 × 1 switches at the input and output ports are realized as BT of 1 × 2 and 2 × 1 switches, the number of necessary 3D edges can be reduced by splitting the vertices of the original K5,5 and placing them into appropriate faces of the spanning maximum planar subgraph depicted in blue. The white dashed squares represent 1 × 2 switches, while the dashed circle with gray filling represents a 2 × 1 switch. This approach allows to replace a pair of 3D edges by a single one. In case where both m and n are odd, the number of missing edges is also odd, and one missing edge (in this case $\{{{v_{N, - 2}},{v_{M,2}}} \}$) must be realized with help of one single 3D edge. (d) Graph drawing of a 4 × 4 SAS circuit, analogous to the case described in (c). In case at least one of the numbers m or n is even, the number of 3D edges can be reduced by a factor of 2 compared to the case when 1 × n and m × 1 switches are realized as LE. For our experimental demonstration, we used the PIC layout displayed in Fig. 2(d), which was obtained in a similar way as Fig. 4(d), with the difference that the auxiliary vertices (1 × 2 switches) in Fig. 2(d) were placed in the outer face of the spanning maximum planar subgraph rather than in its inner face, as displayed here.
Fig. 5.
Fig. 5. Different graph drawings of a facet-coupled 4 × 4 SAS circuit: A first set of vertices (rectangles and half circles) is used to represent facet-coupled optical input and output ports, and a second kind of vertices (squares and full circles) represents the 1 × n or m × 1 switches. Each port vertex is connected to the associated switch vertex by a graph edge that represents the access waveguide (a) Simplistic non-optimum graph representation based on the same approach as the surface-coupled SAS circuit shown in Fig. 2(a). Input and output ports are clustered into two groups of neighboring vertices along the chip boundary. For a 4 × 4 SAS circuit, 36 WGX are required. (b) By interleaving the input and output ports along the chip boundary, the number of crossings can be reduced, leading to a total number of 16 WGX for a 4 × 4 SAS circuit. (c) The number of crossings can also be reduced by allowing routing of waveguides between the ports and the corresponding 1 × n and n × 1 switches, leading to a total number of 20 WGX for the depicted graph drawing. (d) Circuit layout obtained by combining interleaving of input and output ports with routing of waveguides between the ports and the corresponding switches, leading to a total number of 12 WGX.
Fig. 6.
Fig. 6. Circuit layouts for facet-coupled 2D/3D hybrid 4 × 4 SAS. (a) Simple, but not optimal layout, where the 1 × 4 and 4 × 1 switches have been realized as LE. The relation for $\mu _{n,n}^{(\textrm{facet})}$ represents the exact number of WOP in this simplistic implementation. (b) Best found, but not necessarily optimal layout for the case in which the 1 × 4 and 4 × 1 switches have been realized as BT of 1 × 2 and 2 × 1 switches. The relation for $\mu _{n,n}^{(\textrm{facet,}\ \textrm{BT})}$ is an upper bound for the minimum number of WOP.
Fig. 7.
Fig. 7. Drawings of complete bipartite graphs Kn,n with all vertices placed on the closed boundary curve (dashed circular line), and the vertices of two different sets being interleaved along the boundary. Equation (15) gives the local crossing number of such drawing, which occurs along the blue edges that divide the boundary area in two parts such that the number of vertices in both parts is as much balanced as possible. (a) In case n is odd (here: n = 5), both parts contain the same number of vertices. (b) In case n is even (here: n = 6), there is one more vertex of each vertex set in one part.
Fig. 8.
Fig. 8. Different graph drawings of a simplistic model of a facet-coupled 4 × 4 and 5 × 4 SAS circuit: (a) Graph drawing of a 4 × 4 SAS circuit where 1 × 4 and 4 × 1 switches at the input and output ports are LE. (b) Planar-edge-crossing-free graph representation of the same circuit. The edges depicted in blue represent a spanning planar subgraph of K4,4. The remaining edges are realized with help of 3D edges (representing WOP) depicted as dashed red lines. The 3D edges connect to planar edges depicted in black that connect to the vertices in the drawing plane. (c) If the 1 × 5 and 5 × 1 switches at the input and output ports are realized as BT of 1 × 2 and 2 × 1 switches, the number of necessary 3D edges can be reduced by splitting the vertices of the original K4,4 and by placing them into appropriate areas which are defined by the edges of the spanning planar subgraph (blue) and by the x or y coordinate axes. The white dashed squares represent 1 × 2 switches, while the filled gray circle represents a 2 × 1 switch. This approach allows to replace two 3D edges by one. In case where both m and n are even, the number of missing edges is odd, therefore, one missing edge (here: $\{{{v_{N,3}},{v_{M,4}}} \}$) must be realized with help of one single 3D edge (d) Graph drawing of a 5 × 4 SAS circuit, analogous to the case described in (c). In case at least one of the numbers m or n is odd, the number of 3D edges can be reduced exactly 2 times compared to the case when 1 × n and m × 1 switches are realized as LE.

Tables (2)

Tables Icon

Table 1. Quantitative Comparison of Surface-Coupled n × n Switch-and-Select (SAS) Circuit Implementations Based on WGX in Single-Layer Circuits and on WOP in Hybrid 2D/3D Photonic Integrationa

Tables Icon

Table 2. Quantitative Comparison of n × n Facet-Coupled Switch-and-Select (SAS) Circuit Implementations Based on WGX in Single-Layer Circuits and on WOP in Hybrid 2D/3D Photonic Integrationa

Equations (15)

Equations on this page are rendered with MathJax. Learn more.

η n , n ( basic ) = ( n ( n 1 ) 2 ) 2
η n , n ( surf ) = n 2 2 n 1 2 2 .
μ n , n ( surf ) = n 2 ( 4 n 4 ) = ( n 2 ) 2
μ n , n ( surf,   BT ) = ( n 2 ) 2 2 ,
ξ n , n ( surf ) = ( n 2 1 ) 2 ,
cr conj . ( K m , n ) = η m , n ( surf ) = m 2 n 2 m 1 2 n 1 2 ,
lcr conj .   drawing ( K m , n ) = ξ m , n ( surf ) = ( m 2 1 ) ( n 2 1 ) .
μ m , n ( surf ) = m n ( 2 m + 2 n 4 ) = ( m 2 ) ( n 2 )
μ m , n ( surf,   BT ) = ( m 2 ) ( n 2 ) 2 ,
η m , n ( facet,   basic ) = ( m 2 ) ( n 2 ) = ( m ( m 1 ) 2 ) ( n ( n 1 ) 2 ) ,
η m , n ( facet ) = 1 12 n ( m 1 ) ( 2 m n 3 m n ) .
η n , n ( facet ) = 1 6 n 2 ( n 1 ) ( n 2 ) ,
μ m , n ( facet ) = ( m 1 ) ( n 1 ) ,
μ m , n ( facet,   BT ) = ( m 1 ) ( n 1 ) 2 ,
ξ m , n ( facet ) = 2 n 1 2 n 1 2 ,