Abstract

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 231-1 pseudorandom bit sequence optical data with the bit-error rate less than 10−12 at incident optical power of −7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

© 2012 OSA

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  1. T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999).
    [CrossRef]
  2. A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011).
    [CrossRef]
  3. S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005).
    [CrossRef]
  4. B. Nakhkoob, S. Ray, and M. M. Hella, “High speed photodiodes in standard nanometer scale CMOS technology: a comparative study,” Opt. Express20(10), 11256–11270 (2012).
    [CrossRef] [PubMed]
  5. M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
    [CrossRef]
  6. W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, and Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proceedings of IEEE Asian Solid-State Circuits Conference (IEEE, 2007), pp. 396–399.
  7. F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits44(10), 2856–2867 (2009).
    [CrossRef]
  8. T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010).
    [CrossRef]
  9. D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
    [CrossRef]
  10. S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
    [CrossRef]
  11. H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007).
    [CrossRef]
  12. M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express18(23), 24189–24194 (2010).
    [CrossRef] [PubMed]
  13. J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
    [CrossRef]
  14. B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
    [CrossRef]
  15. D. Kucharski, D. Guckenberger, G. Masini, S. Abdalla, J. Witzens, and S. Sahni, “10Gb/s 15mW optical receiver with integrated germanium photodetector and hybrid inductor peaking in 0.13 μm SOI CMOS technology,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2010), pp. 360–361.
  16. J.-S. Youn, M.-J. Lee, K.-Y. Park, H. Rücker, and W.-Y. Choi, “A 12.5-Gb/s SiGe BiCMOS optical receiver with a monolithically integrated 850-nm avalanche photodetector,” in Proceedings of Optical Fiber Communication Conference (2012), paper OM3E2.
  17. M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012).
    [CrossRef]
  18. M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008).
    [CrossRef]

2012

B. Nakhkoob, S. Ray, and M. M. Hella, “High speed photodiodes in standard nanometer scale CMOS technology: a comparative study,” Opt. Express20(10), 11256–11270 (2012).
[CrossRef] [PubMed]

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
[CrossRef]

M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012).
[CrossRef]

2011

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
[CrossRef]

A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011).
[CrossRef]

2010

T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010).
[CrossRef]

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
[CrossRef]

M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express18(23), 24189–24194 (2010).
[CrossRef] [PubMed]

2009

F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits44(10), 2856–2867 (2009).
[CrossRef]

2008

M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008).
[CrossRef]

2007

H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007).
[CrossRef]

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

2005

S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005).
[CrossRef]

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

1999

T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999).
[CrossRef]

Annema, A.-J.

S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005).
[CrossRef]

Barth, R.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Berroth, M.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

Carusone, A. C.

A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011).
[CrossRef]

T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010).
[CrossRef]

Chang, Y.-W.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
[CrossRef]

Chen, W.-Z.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
[CrossRef]

Choi, W.-Y.

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
[CrossRef]

M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012).
[CrossRef]

M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express18(23), 24189–24194 (2010).
[CrossRef] [PubMed]

M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008).
[CrossRef]

H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007).
[CrossRef]

Gaugler, E.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

Grözing, M.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

Han, G.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
[CrossRef]

Han, J.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
[CrossRef]

Heinemann, B.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Hella, M. M.

Huang, S.-H.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
[CrossRef]

Huang, Y.-T.

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
[CrossRef]

Jutzi, M.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

Kang, H.-S.

M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008).
[CrossRef]

H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007).
[CrossRef]

Kao, T.

A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011).
[CrossRef]

Kao, T. S.

T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010).
[CrossRef]

Knoll, D.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Krishnamoorthy, A. V.

T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999).
[CrossRef]

Lee, D.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
[CrossRef]

Lee, M.-J.

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
[CrossRef]

M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012).
[CrossRef]

M.-J. Lee and W.-Y. Choi, “A silicon avalanche photodetector fabricated with standard CMOS technology with over 1 THz gain-bandwidth product,” Opt. Express18(23), 24189–24194 (2010).
[CrossRef] [PubMed]

M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008).
[CrossRef]

H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007).
[CrossRef]

Mazioschek, W.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

Musa, F. A.

T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010).
[CrossRef]

Nakhkoob, B.

Nauta, B.

S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005).
[CrossRef]

Park, K.-Y.

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
[CrossRef]

Park, S. M.

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
[CrossRef]

Radovanovic, S.

S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005).
[CrossRef]

Ray, S.

Rücker, H.

M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012).
[CrossRef]

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Steyaert, M. S. J.

F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits44(10), 2856–2867 (2009).
[CrossRef]

Tavernier, F.

F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits44(10), 2856–2867 (2009).
[CrossRef]

Tillack, B.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Winkler, W.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Woodward, T.-K.

T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999).
[CrossRef]

Yasotharan, H.

A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011).
[CrossRef]

Youn, J.-S.

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
[CrossRef]

Appl. Phys. Lett.

H.-S. Kang, M.-J. Lee, and W.-Y. Choi, “Si avalanche photodetectors fabricated in standard complementary metal-oxide-semiconductor process,” Appl. Phys. Lett.90(15), 151118 (2007).
[CrossRef]

IEEE Electron Device Lett.

M.-J. Lee, H. Rücker, and W.-Y. Choi, “Effects of guard-ring structures on the performance of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Electron Device Lett.33(1), 80–82 (2012).
[CrossRef]

M.-J. Lee, H.-S. Kang, and W.-Y. Choi, “Equivalent circuit model for Si avalanche photodetectors fabricated in standard CMOS process,” IEEE Electron Device Lett.29(10), 1115–1117 (2008).
[CrossRef]

IEEE J. Quantum Electron.

J.-S. Youn, M.-J. Lee, K.-Y. Park, and W.-Y. Choi, “10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector,” IEEE J. Quantum Electron.48(2), 229–236 (2012).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron.

T.-K. Woodward and A. V. Krishnamoorthy, “1-Gb/s integrated optical detectors and receivers in commercial CMOS technologies,” IEEE J. Sel. Top. Quantum Electron.5(2), 146–156 (1999).
[CrossRef]

IEEE J. Solid-state Circuits

A. C. Carusone, H. Yasotharan, and T. Kao, “CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors,” IEEE J. Solid-state Circuits46(8), 1832–1842 (2011).
[CrossRef]

S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication,” IEEE J. Solid-state Circuits40(8), 1706–1717 (2005).
[CrossRef]

F. Tavernier and M. S. J. Steyaert, “High-speed optical receivers with integrated photodiode in 130 nm CMOS,” IEEE J. Solid-state Circuits44(10), 2856–2867 (2009).
[CrossRef]

D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-state Circuits45(12), 2861–2873 (2010).
[CrossRef]

S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-state Circuits46(5), 1158–1169 (2011).
[CrossRef]

IEEE Photon. Technol. Lett.

M. Jutzi, M. Grözing, E. Gaugler, W. Mazioschek, and M. Berroth, “2-Gb/s CMOS optical integrated receiver with a spatially modulated photodetector,” IEEE Photon. Technol. Lett.17(6), 1268–1270 (2005).
[CrossRef]

IEEE Trans. Circuits Syst. I Regul. Pap.

T. S. Kao, F. A. Musa, and A. C. Carusone, “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I Regul. Pap.57(11), 2844–2857 (2010).
[CrossRef]

Opt. Express

Semicond. Sci. Technol.

B. Heinemann, R. Barth, D. Knoll, H. Rücker, B. Tillack, and W. Winkler, “High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches,” Semicond. Sci. Technol.22(1), 153–157 (2007).
[CrossRef]

Other

D. Kucharski, D. Guckenberger, G. Masini, S. Abdalla, J. Witzens, and S. Sahni, “10Gb/s 15mW optical receiver with integrated germanium photodetector and hybrid inductor peaking in 0.13 μm SOI CMOS technology,” in Proceedings of IEEE International Solid-State Circuits Conference (IEEE, 2010), pp. 360–361.

J.-S. Youn, M.-J. Lee, K.-Y. Park, H. Rücker, and W.-Y. Choi, “A 12.5-Gb/s SiGe BiCMOS optical receiver with a monolithically integrated 850-nm avalanche photodetector,” in Proceedings of Optical Fiber Communication Conference (2012), paper OM3E2.

W.-Z. Chen, S.-H. Huang, G.-W. Wu, C.-C. Liu, Y.-T. Huang, C.-F. Chiu, W.-H. Chang, and Y.-Z. Juang, “A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer,” in Proceedings of IEEE Asian Solid-State Circuits Conference (IEEE, 2007), pp. 396–399.

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