Abstract

We report a broadband digital electro-optical switch, based upon a multi-stage Mach-Zehnder lattice design in silicon-on-insulator. A digital switching response is demonstrated, engineered through apodization of the coupling coefficients between stages. The digital switching behavior results in crosstalk lower than −15 dB for drive-voltage noise levels in excess of 300 mVpp, which exceeds the noise tolerance of a conventional single-stage Mach-Zehnder switch by more than six-fold. In addition, the digital design enables a larger maximum ‘on’-state extinction (below −26 dB) and lower ‘on’-state free-carrier-induced insertion loss (less than 0.45 dB) than that of the single-stage switch. The noise-tolerant, low-crosstalk switch can thus play a key role within CMOS-integrated reconfigurable optical networks operating under noisy on-chip conditions.

© 2011 OSA

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2011 (2)

2009 (6)

J. Van Campenhout, W. M. J. Green, X. Liu, S. Assefa, R. M. Osgood, and Y. A. Vlasov, “Silicon-nitride surface passivation of submicrometer silicon waveguides for low-power optical switches,” Opt. Lett. 34(10), 1534–1536 (2009).
[CrossRef] [PubMed]

J. Van Campenhout, W. M. J. Green, and Y. A. Vlasov, “Design of a digital, ultra-broadband electro-optic switch for reconfigurable optical networks-on-chip,” Opt. Express 17(26), 23793–23808 (2009).
[CrossRef]

J. Van Campenhout, W. M. J. Green, S. Assefa, and Y. A. Vlasov, “Low-power, 2 x 2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks,” Opt. Express 17(26), 24020–24029 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

2008 (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

2005 (1)

E. Alon, V. Stojanovic, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-state Circuits 40(4), 820–828 (2005).
[CrossRef]

1987 (1)

R. A. Soref and B. R. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23(1), 123–129 (1987).
[CrossRef]

Ahn, J.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Alon, E.

E. Alon, V. Stojanovic, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-state Circuits 40(4), 820–828 (2005).
[CrossRef]

Asanovic, K.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Assefa, S.

Batten, C.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Beausoleil, R. G.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Bennett, B. R.

R. A. Soref and B. R. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23(1), 123–129 (1987).
[CrossRef]

Bergman, K.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Binkert, N.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Cunningham, J. E.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Davis, A.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Doany, F. E.

Fattal, D.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Fiorentino, M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Green, W. M. J.

Ho, R.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Holzwarth, C. W.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Horowitz, M. A.

E. Alon, V. Stojanovic, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-state Circuits 40(4), 820–828 (2005).
[CrossRef]

Hoyt, J. L.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Jahnes, C. V.

John, R. A.

Joshi, A.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Jouppi, N. P.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Kartner, F. X.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Kash, J. A.

Khilo, A.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Koka, P.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Krishnamoorthy, A. V.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Lee, B. G.

Lexau, J.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Li, G. L.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Li, H. Q.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Liu, X.

McLaren, M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Moss, B.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Orcutt, J.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Osgood, R. M.

Popovic, M. A.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Ram, R. J.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Rylyakov, A. V.

Santori, C. M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Schow, C. L.

Schreiber, R. S.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Schwetman, H.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Shubin, I.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Smith, H. I.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Soref, R. A.

R. A. Soref and B. R. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23(1), 123–129 (1987).
[CrossRef]

Spillane, S. M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Stojanovic, V.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

E. Alon, V. Stojanovic, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-state Circuits 40(4), 820–828 (2005).
[CrossRef]

Van Campenhout, J.

Vantrease, D.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Vlasov, Y. A.

Xu, Q.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Yang, M.

Zheng, X. Z.

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Appl. Phys., A Mater. Sci. Process. (1)

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

IEEE J. Quantum Electron. (1)

R. A. Soref and B. R. Bennett, “Electrooptical effects in silicon,” IEEE J. Quantum Electron. 23(1), 123–129 (1987).
[CrossRef]

IEEE J. Solid-state Circuits (1)

E. Alon, V. Stojanovic, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE J. Solid-state Circuits 40(4), 820–828 (2005).
[CrossRef]

IEEE Micro (1)

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-dram networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

J. Lightwave Technol. (1)

Opt. Express (3)

Opt. Lett. (1)

Proc. IEEE (1)

A. V. Krishnamoorthy, R. Ho, X. Z. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97(7), 1337–1361 (2009).
[CrossRef]

Other (3)

A. Biberman, H. L. R. Lira, K. Padmaraju, N. Ophir, M. Lipson, and K. Bergman, “Broadband CMOS-compatible silicon photonic electro-optic switch,” in Proceedings of Conf. Lasers Electro-Optics (CLEO)2010, paper CPDA11, May 2010.

W. M. J. Green, S. Assefa, A. Rylyakov, C. Schow, F. Horst, and Y. A. Vlasov, “CMOS integrated silicon nanophotonics: enabling technology for exascale computational systems,” presented at SEMICON 2010, Chiba, Japan, 1–3 December, 2010.

S. Assefa, W. M. J. Green, A. Rylyakov, C. Schow, F. Horst, and Y. A. Vlasov, “CMOS integrated silicon nanophotonics: enabling technology for exascale computational systems,” in Proceedings of the Optical Fiber Communication Conference, (Optical Society of America, 2011) paper OMM6; See also http://www.research.ibm.com/photonics .

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Figures (6)

Fig. 1
Fig. 1

(a) Schematic representation of the four-stage MZL switch, featuring Hamming-apodized coupling coefficients (κ1 = 3.2%, κ2 = 13.1% and κ3 = 20.5%). (b) Microscope image of the fabricated device, which occupies a total footprint of 160 μm x 75 μm. The directional-coupler lengths are respectively L1 = 4.1 μm, L2 = 8.5 μm, and L3 = 10.8 μm. Each of the four p-i-n diode phase shifters in the lower active branch is 50-μm long. The top branch contains shorted dummy p-i-n diodes. The nodes connected to the signal and ground electrodes are illustrated by dashed lines and black dots. The scale bar is 30-μm long.

Fig. 2
Fig. 2

(a) Calculated switching response of the four-stage MZL switch as shown in Fig. 1(a), as a function of injected-carrier density. The T12 switching sidelobes are suppressed to less than −20 dB. (b) Calculated switching response of the reference MZ switch.

Fig. 3
Fig. 3

(a) T11 and T12 transmittance spectra of the four-stage MZL switch, measured for a continuous-wave applied voltage VD = 0 V (‘off’) and VD = 1.3 V (‘on’). Crosstalk levels lower than −17 dB are obtained in the ‘off’-state, whereas better than −26 dB crosstalk levels are obtained in the ‘on’-state (at 1478 nm). (b) Transmittance spectra of the reference MZ switch. Crosstalk levels of about −20 dB are obtained for both the ‘off’-state (VD = 0 V), and the ‘on’-state (VD = 1.1 V), each at 1530 nm.

Fig. 4
Fig. 4

(a) Switching response of a four-stage MZL switch as a function of applied voltage, measured for 80-ns-long pulses with a 2-% duty cycle. More than −15 dB extinction of T12 is obtained for VD > 1.16 V, and more than −20 dB for 1.18 V < VD < 1.28 V. Despite a switching sidelobe with only −16 dB extinction at VD = 1.37 V, a digital switching response is obtained. (b) Analog switching response of the reference MZ switch. The ‘on’-state, showing more than −20 dB extinction of T12, is reached at VD = 1.1 V. The noise floor of the measurements in both (a) and (b) is −21 dB. For voltages in the range 0-0.6 V, the switching response remains essentially flat due to the electrical turn-on characteristics of the p-i-n diode phase-shifter.

Fig. 5
Fig. 5

(a) Time-resolved T12 transmittance waveforms for the four-stage MZL switch, measured for 150-ns-long, drive pulses with Von = 1.25 V and various amplitudes of added voltage noise. For 300 mVpp voltage noise, the worst-case T12 extinction is as low as −7 dB. (b) Noisy applied switching waveform, where the noise consists of a 500-MHz 27-1 PRBS signal with variable peak-to-peak amplitude Vpp. (c) Overview of the worst-case T12 transmittance as a function of voltage noise Vpp, comparing the reference MZ switch and the four-stage MZL switch biased at Von = 1.25 V as well as at Von = 1.5 V. At −15 dB extinction, the noise tolerance of the MZ is 50 ± 5 mVpp, and that of the MZL is 140 ± 14 mVpp, for Von = 1.25 V. The noise tolerance at −15 dB increases to more than 300 ± 30 mVpp for Von = 1.5V.

Fig. 6
Fig. 6

Bit-error-rate (BER) curves measured for the four-stage MZL switch using a 40 Gbps 27-1 PRBS optical data stream, both for T12 transmission in the ‘off’-state (blue), as well as for T11 transmission in the ‘on’-state (Von = 1.3 V, continuous-wave drive, green). A BER below 10−10 can be obtained for both transmission paths. The orange data set shows the BER curve recorded for T11 transmission at Von = 1.3 V with 200 mVpp of added noise. A BER below 10−10 can still be obtained, albeit with a 0.7 ± 0.2 dB power penalty. The insets show 40 Gbps 231-1 PRBS eye diagrams for the respective transmitted optical data streams, recorded for 3 mW of received optical power. The black scale bar represents a 20 ps time interval.

Tables (1)

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Table 1 Comparison of Measured Switching Characteristics of the MZL and MZ Switch

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