Abstract

We present a 1x4 reconfigurable demultiplexing filter based on cascaded thermally tunable silicon racetrack resonators with ultralow tuning powers. The use of free-standing silicon resonators with undercut structures significantly reduces the tuning power, with a figure of ~2.9 mW per free spectral range. Even with the presence of thermal crosstalk between two adjacent resonators, we demonstrate multiplexing functionality for channel spacings of 200 GHz, 100 GHz, and 50 GHz, with channel wavelengths aligned to International Telecommunication Union (ITU) grid specifications. Crosstalk values for 200 GHz and 50 GHz channel spacings are less than −20 dB and −11.5 dB, respectively. The total power to achieve this performance is in the range of 1.84 mW to 2.4 mW. Such low-power, compact, and reconfigurable filters are particularly useful in chip-scale optical interconnects.

© 2010 OSA

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    [CrossRef]
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2010

2009

M. Geng, L. Jia, L. Zhang, L. Yang, P. Chen, T. Wang, and Y. Liu, “Four-channel reconfigurable optical add-drop multiplexer based on photonic wire waveguide,” Opt. Express 17(7), 5502–5516 (2009).
[CrossRef] [PubMed]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

2008

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

2007

2006

R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

2004

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Ahn, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Ahn, J.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Apsel, A. B.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Asanovic, K.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Asghari, M.

Baba, T.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Baets, R.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Batten, A.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Beals, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Beausoleil, R. G.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Bergman, K.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Binkert, N.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Bogaerts, W.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Brouckaert, J.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Carothers, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Chen, P.

Chen, Y.-K.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Conway, T.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Cunningham, J. E.

P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Davis, A.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Dong, P.

Dumon, P.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Fattal, D.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Feng, D.

Feng, N.-N.

Fiorentino, M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Fukazawa, T.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Geng, M.

Gill, D. M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Green, W. M. J.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Grove, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Ho, R.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Holzwarth, W.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Hong, C.-Y.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Horst, F.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Hoyt, J. L.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Jalali, B.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

Jia, L.

Joshi, J.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Jouppi, N. P.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Kartner, F. X.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Khan, M. H.

Khilo, B.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Kimerling, L. C.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Koka, P.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Krishnamoorthy, A. V.

Lexau, J.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Li, D.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Li, G.

P. Dong, W. Qian, H. Liang, R. Shafiiha, D. Feng, G. Li, J. E. Cunningham, A. V. Krishnamoorthy, and M. Asghari, “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Opt. Express 18(19), 20298–20304 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Li, H. Q.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Liang, H.

Lipson, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Liu, J.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Liu, Y.

Martinez, J.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

McLaren, M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Michel, J.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
[CrossRef]

Moss, C.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Ng, H.-Y.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Offrein, B. J.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Ohno, F.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Orcutt, A.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Pan, D.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Panepucci, R. R.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Paniccia, M.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

Patel, S. S.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Pathak, K.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Pomerene, A. T.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Popovic, M. A.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Qi, M.

Qian, W.

Ram, R. J.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Rasras, M.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Reed, G.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

Santori, C. M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Schreiber, R. S.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Schwetman, H.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Selvaraja, S.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Shafiiha, R.

Shen, H.

Shubin, I.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Smith, H. I.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Soref, R. A.

R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

Sparacin, D. K.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Spillane, S. M.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Stojanovic, V.

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

Tu, K.-Y.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Van Thourhout, D.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

Vantrease, D.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Vlasov, Y. A.

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

Wang, M. R.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Wang, T.

Wang, X.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

White, A. E.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Wong, C. W.

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Xiao, S.

Xu, Q.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

Yang, L.

Zhang, L.

Zheng, X.

P. Dong, W. Qian, H. Liang, R. Shafiiha, N.-N. Feng, D. Feng, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, “Low power and compact reconfigurable multiplexing devices based on silicon microring resonators,” Opt. Express 18(10), 9852–9858 (2010).
[CrossRef] [PubMed]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Appl. Phys., A Mater. Sci. Process.

J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Appl. Phys., A Mater. Sci. Process. 95(4), 989–997 (2009).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron.

R. A. Soref, “The past, present and future of silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 12(6), 1678–1687 (2006).
[CrossRef]

IEEE Micro

A. Batten, J. Joshi, A. Orcutt, B. Khilo, C. Moss, W. Holzwarth, M. A. Popovic, H. Q. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, “Building many-more processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro 29(4), 8–21 (2009).
[CrossRef]

IEEE Microw. Mag.

B. Jalali, M. Paniccia, and G. Reed, “Silicon photonics,” IEEE Microw. Mag. 7(3), 58–68 (2006).
[CrossRef]

IEEE Photon. Technol. Lett.

J. Brouckaert, W. Bogaerts, S. Selvaraja, P. Dumon, R. Baets, and D. Van Thourhout, “Planar concave grating demultiplexer with high reflective Bragg reflector facets,” IEEE Photon. Technol. Lett. 20(4), 309–311 (2008).
[CrossRef]

F. Horst, W. M. J. Green, B. J. Offrein, and Y. A. Vlasov, “Silicon-on-insulator echelle grating WDM demultiplexers with two stigmatic points,” IEEE Photon. Technol. Lett. 21(23), 1743–1745 (2009).
[CrossRef]

IEEE Trans. Comput.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput. 57(9), 1246–1260 (2008).
[CrossRef]

Jpn. J. Appl. Phys.

T. Fukazawa, F. Ohno, and T. Baba, “Very compact arrayed-waveguide grating demultiplexer using Si photonic wire waveguides,” Jpn. J. Appl. Phys. 43(No. 5B), L673–L675 (2004).
[CrossRef]

Opt. Eng.

H.-Y. Ng, M. R. Wang, D. Li, X. Wang, J. Martinez, R. R. Panepucci, and K. Pathak, “4 x 4 wavelength-reconfigurable photonic switch based on thermally tuned silicon microring resonators,” Opt. Eng. 47(4), 044601 (2008).
[CrossRef]

Opt. Express

Proc. IEEE

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE 97, 1166–1185 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE 97, 1337–1361 (2009).
[CrossRef]

Proc. SPIE

L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic–photonic integrated circuits on the CMOS platform,” Proc. SPIE 6125, 6–15 (2006).

Other

F. Gan, T. Barwicz, M. A. Popovic, M. S. Dahlem, C. W. Holzwarth, P. T. Rakich, H. I. Smith, E. P. Ippen, and F. X. Kartner, “Maximizing the thermo-optic tuning range of silicon photonic structures,” in Photonics in Switching (2007), pp. 67–68.

M. S. Dahlem, C. W. Holzwarth, A. Khilo, F. X. Kartner, H. I. Smith, and E. P. Ippen, “Eleven-channel Second-order silicon microring-resonator filterbank with tunable channel spacing,” in Proceedings of Conference on Lasers and Electro-Optics (CLEO/QELS 2010), paper CMS5.

C. T. DeRose, M. R. Watts, D. C. Trotter, D. L. Luck, G. N. Nielson, and R. W. Young, “Silicon microring modulator with integrated heater and temperature sensor for thermal control,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2010), paper CThJ3.

Q. Xu, “Silicon modulator based on coupled microring resonators,” in Integrated Photonics Research, Silicon and Nanophotonics (OSA 2010), paper IWA3.

D. Geuzebroek, E. J. Klein, H. Kelderman, and A. Driessen, “Wavelength tuning and switching of a thermooptic microring resonator,” Proc. ECIO, pp. 395–398 (2003).

M. R. Watts, W. A. Zortman, D. C. Trotter, G. N. Nielson, D. L. Luck, and R. W. Young, “Adiabatic Resonant Microrings (ARMs) with directly integrated thermal microphotonics,” in Proceedings of Conference on Quantum electronics and Laser Science Conference (CLEO/QELS 2009), pp. 1 – 2.

J. E. Cunningham, I. Shubin, X. Zheng, T. Pinguet, A. Mekis, and A. V. Krishnamoorthy, “Highly-efficient thermally-tuned resonant filters,” IEEE Summer Topical Meet. On Optical Networks and Devices for Data Centers 18, 8406–8411 (2010).

M. Popovic, Theory and design of high-index-contrast microphotonic circuits, PhD thesis, (MIT 2008).

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Figures (4)

Fig. 1
Fig. 1

Tilted top-view SEM for a fully fabricated WDM filter using free-standing resonators.

Fig. 2
Fig. 2

Drop port spectra for resonators 1-4 (a-d) with various heating powers on resonator 1.

Fig. 3
Fig. 3

(a) Drop port spectra before tuning. (b) Drop port spectra after thermal tuning to achieve 200 GHz channel spacing.

Fig. 4
Fig. 4

Drop port spectra after thermal tuning to achieve 100 GHz (a) and 50 GHz (b) channel spacing.

Tables (1)

Tables Icon

Table 1 Measured thermal efficiency

Equations (2)

Equations on this page are rendered with MathJax. Learn more.

Δ λ = C P
P = C 1 Δ λ

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