Abstract

We preset a new method to optically represent and implement binary logic, and we implement some unforced logic gates. The binary logic zero and one are taken to be an optical beam, or any electromagnetic wave, that is polarized at a selected state and its negation, orthogonal counterpart, or otherwise. In one implementation, a thin-film system is then designed and used so as it can move between 2 positions producing the net desired polarization change of the output. The output consists of a wave that is polarized either in the direction of the original logic 1 or 0 or any other chosen state and its negation, orthogonal counterpart. The system can be cascaded infinitely due to the fact that the output and input are both of the same format and that the logic zero and one are not dependant on the intensity of the input or the output light beam. The unforced gates exclusive OR and exclusive NOR along with a simple inverter are demonstrated in this communication. We present three design architectures, where each has two types of gates. In one type of gates the polarization state magnitude can carry information that can be employed for testability or reverse logic. XOR, XNOR, and inverter gate designs and operation are discussed in detail, and an easy-to-follow step-by-step algorithm is presented. The introduced architectures are easily adapted for simultaneous cascading, multiple input designs, and integrated optical architecture. * Patent Pending

© 2006 Optical Society of America

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References

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    [CrossRef]
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2005 (1)

2003 (1)

1997 (1)

R. Torroba, R. Henao, and C. Carletti, "Polarization encoded architecture for optical logic operations," Optik 107, 41 - 43 (1997).

1996 (1)

1995 (1)

F. Yu and G. Zheng, "An improved polarization-encoded logic algebra (PLA) used for the design of an optical logic gate for a 2D data array: theory," Opt. Commun. 115, 585 - 596 (1995).
[CrossRef]

1994 (1)

H. Peng, L. Liu, Y. Yin, and Z Wang, "Integrated polarization-optical logic processor," Opt. Commun. 112, 131 - 135 (1994).
[CrossRef]

1993 (2)

M. S. Alam and M. A. Karim, "Multiple-valued logic based multiprocessor using polarization-encoded optical shadow-casting," Opt. Commun. 96, 164 -173 (1993).
[CrossRef]

W. Wu, S. Campbell, S. Zhou, and P. Yeh, "Polarization-encoded optical logic operations in photorefractive media," Opt. Lett. 18, 1742 - 1744 (1993).
[CrossRef] [PubMed]

1992 (2)

1990 (1)

1989 (1)

1987 (3)

1986 (1)

1975 (1)

Ahmed, J. U.

Alam, M. S.

M. S. Alam and M. A. Karim, "Multiple-valued logic based multiprocessor using polarization-encoded optical shadow-casting," Opt. Commun. 96, 164 -173 (1993).
[CrossRef]

Awatsuji, Y.

Awwal, A. A. S.

Azzam, R. M. A.

Bashara, N. M.

Berzett, W. A.

Campbell, S.

Carletti, C.

R. Torroba, R. Henao, and C. Carletti, "Polarization encoded architecture for optical logic operations," Optik 107, 41 - 43 (1997).

R. Torroba, R. Henao, and C. Carletti, "Digital polarization-encoding technique for optical logic operations," Opt. Lett. 21, 1918 - 1920 (1996).
[CrossRef] [PubMed]

Cathey, W. T.

Cherri, A. K.

Habli, M. A.

M. A. Habli and K. Leonik, "Polarization-coded optical logic gates for N-inputs," Optik 91, 100 - 102 (1992).

Handschy, M. A.

Henao, R.

R. Torroba, R. Henao, and C. Carletti, "Polarization encoded architecture for optical logic operations," Optik 107, 41 - 43 (1997).

R. Torroba, R. Henao, and C. Carletti, "Digital polarization-encoding technique for optical logic operations," Opt. Lett. 21, 1918 - 1920 (1996).
[CrossRef] [PubMed]

Johnson, K. M.

Karim, M. A.

M. S. Alam and M. A. Karim, "Multiple-valued logic based multiprocessor using polarization-encoded optical shadow-casting," Opt. Commun. 96, 164 -173 (1993).
[CrossRef]

M. A. Karim, A. A. S. Awwal, and A. K. Cherri, "Polarization-encoded optical shadow-casting logic units: design," Appl. Opt. 26, 2720 - 2725 (1987).
[CrossRef] [PubMed]

Keeling, D. A.

Kubota, T.

Kumar, G. R.

Leonik, K.

M. A. Habli and K. Leonik, "Polarization-coded optical logic gates for N-inputs," Optik 91, 100 - 102 (1992).

Liu, L.

H. Peng, L. Liu, Y. Yin, and Z Wang, "Integrated polarization-optical logic processor," Opt. Commun. 112, 131 - 135 (1994).
[CrossRef]

Lohmann, A. W.

Mason, J. S.

Nishimura, N.

Pagano-Stauffer, L. A.

Peng, H.

H. Peng, L. Liu, Y. Yin, and Z Wang, "Integrated polarization-optical logic processor," Opt. Commun. 112, 131 - 135 (1994).
[CrossRef]

Rao, K. D.

Sharma, K. K.

Singh, B. P.

Torroba, R.

R. Torroba, R. Henao, and C. Carletti, "Polarization encoded architecture for optical logic operations," Optik 107, 41 - 43 (1997).

R. Torroba, R. Henao, and C. Carletti, "Digital polarization-encoding technique for optical logic operations," Opt. Lett. 21, 1918 - 1920 (1996).
[CrossRef] [PubMed]

Wang, Z

H. Peng, L. Liu, Y. Yin, and Z Wang, "Integrated polarization-optical logic processor," Opt. Commun. 112, 131 - 135 (1994).
[CrossRef]

Weigelt, J.

Wu, W.

Yeh, P.

Yin, Y.

H. Peng, L. Liu, Y. Yin, and Z Wang, "Integrated polarization-optical logic processor," Opt. Commun. 112, 131 - 135 (1994).
[CrossRef]

Yousef, M. S. A.

Yu, F.

F. Yu and G. Zheng, "An improved polarization-encoded logic algebra (PLA) used for the design of an optical logic gate for a 2D data array: theory," Opt. Commun. 115, 585 - 596 (1995).
[CrossRef]

Zaghloul, A. R. M.

Zheng, G.

F. Yu and G. Zheng, "An improved polarization-encoded logic algebra (PLA) used for the design of an optical logic gate for a 2D data array: theory," Opt. Commun. 115, 585 - 596 (1995).
[CrossRef]

Zhou, S.

Appl. Opt. (5)

J. Opt. Soc. Am. (1)

J. Opt. Soc. Am. A (2)

Opt. Commun. (3)

F. Yu and G. Zheng, "An improved polarization-encoded logic algebra (PLA) used for the design of an optical logic gate for a 2D data array: theory," Opt. Commun. 115, 585 - 596 (1995).
[CrossRef]

M. S. Alam and M. A. Karim, "Multiple-valued logic based multiprocessor using polarization-encoded optical shadow-casting," Opt. Commun. 96, 164 -173 (1993).
[CrossRef]

H. Peng, L. Liu, Y. Yin, and Z Wang, "Integrated polarization-optical logic processor," Opt. Commun. 112, 131 - 135 (1994).
[CrossRef]

Opt. Lett. (4)

Optik (2)

R. Torroba, R. Henao, and C. Carletti, "Polarization encoded architecture for optical logic operations," Optik 107, 41 - 43 (1997).

M. A. Habli and K. Leonik, "Polarization-coded optical logic gates for N-inputs," Optik 91, 100 - 102 (1992).

Other (3)

A. R. M. Zaghloul, M. Elshazly-Zaghloul, W. A. Berzett, and D. A. Keeling, "Thin film coatings: A transmission ellipsometric function (TEF) approach I. Non-negative transmission systems, polarization-devices, coatings, and closed-form design formulae," Appl. Opt., Submitted for publication.
[PubMed]

D. Clarke and J. F. Grainger, Polarized light and optical measurement (Pergamon, New York, 1971).

Y. A. Zaghloul and A. R. M. Zaghloul, "Complete all-optical-processing polarization-based binary-logic representation, gates, and optical processors," Opt. Express, Submitted for publication.

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Figures (12)

Fig. 1.
Fig. 1.

General two-electronic-signal (TES) binary gate architecture is constructed of a collection of optical devices that are cascaded together. Each device is a thin-film polarization device, or an electro-optic device, that is designed to take two states.

Fig. 2.
Fig. 2.

TES architecture, where the input and output beams are parallel. ρ = ρ1ρ2.

Fig. 3.
Fig. 3.

TES architecture, where the input and output beams are collinear. ρ = ρ1 ρ2ρ3

Fig. 4.
Fig. 4.

Complex ρ plane representation of the TES R-gate.

Fig. 5
Fig. 5

Complex ρ plane representation of the TES LPP-gate.

Fig. 6.
Fig. 6.

One possible realization of Table 2 using a film-substrate system.

Fig. 7.
Fig. 7.

A second possible realization of Table 2 using a film-substrate system.

Fig. 8.
Fig. 8.

Complex ρ plane representation of the SES-gate architecture.

Fig. 9.
Fig. 9.

Complex ρ plane representation of the single-reflection single-electronic-signal (SRSES) R-gate architecture.

Fig. 10.
Fig. 10.

Complex ρ plane representation of the single-reflection single-electronic-signal (SRSES) LPP-gate architecture.

Fig. 11.
Fig. 11.

Special case of C and Ć coinciding with the points (+1, 0) and (-1, 0), respectively, in the complex ρ plane, is an intersection case between the R and LPP designs architectures.

Fig. 10.
Fig. 10.

Complex ρ plane representation of ρ-gate architecture.

Tables (14)

Tables Icon

Table 1. Gate-design table, which includes the truth table and the constructed operation table of the R-gate type of the TES architecture of Fig. 4; XOR gate.

Tables Icon

Table 2. Gate design parameters (transformations) derived from Table 1., for the two film-substrate systems TFS1 and TFS2, for the two control states 1 and 0 of each; for an XOR R-gate of the two-electronic-signal (TES)

Tables Icon

Table 3. Same as in Table 1., but for an XNOR TES-architecture R-gate.

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Table 4. Same as in Table 2., but for an XNOR TES-architecture R-gate.

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Table 5. Same as in Table 1, but for a TES-architecture LPP-gate type; XOR.

Tables Icon

Table 6. Same as in Table 2., but for an XNOR TES-architecture R-gate.

Tables Icon

Table 7. Same as in Table 1., but for the single-reflection single-electronic-signal SRSES architecture R-gate, XOR gate, where LBI (LBO) is the laser beam input (output) polarization state; Fig. 9.

Tables Icon

Table 8. Same as in Table 2., but for single-reflection single-electronic-signal (SRSES) architecture R-gate; XOR gate.

Tables Icon

Table 9. Same as in Table 1., but for the SRSES architecture LPP-gate, XOR gate, where LBI (LBO) is the laser beam input (output) polarization state; Fig. 10.

Tables Icon

Table 10. Same as in Table 2., but for the SRSES-architecture LPP-gate, XOR gate; Fig. 10.

Tables Icon

Table 11. Same as in Table 1., but for the SRSES-architecture LPP45-gate, XOR gate, where LBI (LBO) is the laser beam input (output) polarization state; Fig. 11.

Tables Icon

Table 12. Same as in Table 2., but for the SRSES-architecture linearly-polarized light at ± 45° (LPP45), XOR gate; Fig. 11.

Tables Icon

Table 13. Same as in Table 1., but for the SRSES architecture p-gate; XOR gate; Fig. 12.

Tables Icon

Table 14. Same as in Table 2., but for the SRSES-architecture ρ-gate, XOR gate; Fig. 12.

Equations (3)

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ρ = R p R s = tan ψ exp ( ) ,
RI = ( R p 2 + R s 2 ) 2 ,
ρ 1 * ρ 2 = 0 ,

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