On-chip silicon shallowly etched TM<sub>0</sub>-to-TM<sub>1</sub> mode-order converter with high conversion efficiency and low modal crosstalk

Yin Xu; Chenxi Zhu; Xin Hu; Yue Dong; Bo Zhang; Yi Ni

doi:10.1364/JOSAB.387698

Journal of the Optical Society of America B
Vol. 37,
Issue 5,
pp. 1290-1297
(2020)
•https://doi.org/10.1364/JOSAB.387698

On-chip silicon shallowly etched TM₀-to-TM₁ mode-order converter with high conversion efficiency and low modal crosstalk

Yin Xu, Chenxi Zhu, Xin Hu, Yue Dong, Bo Zhang, and Yi Ni

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Yin Xu, Chenxi Zhu, Xin Hu, Yue Dong, Bo Zhang, and Yi Ni, "On-chip silicon shallowly etched TM₀-to-TM₁ mode-order converter with high conversion efficiency and low modal crosstalk," J. Opt. Soc. Am. B 37, 1290-1297 (2020)

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- Wave Guiding and Confinement
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About this Article
History
- Original Manuscript: January 7, 2020
- Revised Manuscript: March 11, 2020
- Manuscript Accepted: March 11, 2020
- Published: April 7, 2020

Abstract

Ever-increasing capacity requirements of optical interconnects drive the emergence and fast development of mode-division-multiplexing (MDM) transmission on-chip, where efficient mode control and conversion components become indispensable. Here, we propose an on-chip silicon ${\text{TM}_0} \mbox{-} \text{to}\mbox {-} {\text{TM}_1}$ mode-order converter by leveraging shallowly etched rectangular slots on the top surface of silicon nanowire. The mode conversion region consists of two rectangular slots on the same side of a silicon nanowire and a smaller one between them to realize the efficient mode-order conversion from input ${\text{TM}_0}$ to output ${\text{TM}_1}$ mode with the help of multimode interference and accumulated phase difference. By studying the etching pattern on the silicon nanowire in detail, we have achieved an on-chip ${\text{TM}_0} \mbox{-} \text{to}\mbox {-} {\text{TM}_1}$ mode-order converter with a high conversion efficiency of 97.5% and low modal crosstalk ${ \lt }{-} {23}\;\text{dB}$ in a conversion length of 11.8 µm; further, the insertion loss is only 0.29 dB at the wavelength of 1.55 µm. Moreover, the device working bandwidth and fabrication tolerance are also analyzed. Note that the proposed shallowly etched slots on the silicon nanowire can also be further developed to achieve the on-chip ${\text{TM}_0} \mbox{-} \text{to} \mbox{-} {\text{TM}_2}$ mode-order conversion. With these characteristics, such a device could boost the development of MDM transmission on-chip with more TM-polarized mode channels.

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${TM}_{0} - to - {TM}_{1}$	$L_{1}$	$L_{2}$	$L_{3}$	$L_{4}$	$L_{5}$	$W$	$W_{1}$	$W_{2}$	$W_{3}$	$W_{4}$	$H_{1}$	$H_{2}$	$H_{3}$
Value (nm)	3900	1780	4200	1150	770	1400	570	170	490	470	300	300	50

Structure	Function	Length (µm)	CE (%)	MC (dB)	IL (dB)	BW (nm)
MZI [10]	${TE}_{0} - to - {TE}_{1} (E)$	$\sim 60$	-	$< - 20$	$\sim 2$	-
Bragg grating [11]	${TE}_{1} - to - {TE}_{2} (E)$	$\sim 130$	-	$< - 19$	0.2	23 (3 dB BW of CS)
Tilted SWG [12]	${TE}_{0} - to - {TE}_{1} / {TE}_{2} (E)$	5.75/6.736	-	$< - 10$	$< 1$	20 ( $MC < - 10 dB$ )
HRIM [13]	${TE}_{0} - to - {TE}_{1} [S]$	1.5	$\sim 90$	-	0.5	$100 (IL < 0.6 dB)$
Ge/Si pattern [14]	${TE}_{0} - to - {TE}_{1} [S]$	1.55	$> 98$	-	$\sim 0.1$	$100 (CE > 92 %)$
Fully etched slot [21]	${TE}_{0} - to - {TE}_{1} [S]$	5.3	$> 90$	-	$< 0.5$	$100 (CE > 90 %)$
Deeply etched slot [22]	${TE}_{0} - to - {TE}_{1} / {TE}_{2} [S]$	$\sim 24 / \sim 8$	$> 97.6$	$< - 20$	-	$> 100 (MC < - 20 dB & CE > 97 %)$
Deeply etched slot [22]	${TE}_{1} - to - {TE}_{3} / {TE}_{2} [S]$	$\sim 6 / \sim 18$	-	-	-	$> 100 (MC < - 20 dB & CE > 97 %)$
$Si - {Si}_{3} N_{4}$ phase plate [24]	${TE}_{0} - to - {TE}_{1} [S]$	$\sim 1.5$	-	−12.8	1.5	-
$Si - {Si}_{3} N_{4}$ phase plate [24]	${TM}_{0} - to - {TM}_{1} [S]$	$\sim 2$	-	−10.6	2.58	-
Silicon metasurface [25]	${TE}_{0} - to - {TE}_{1} [E]$	1.6	$\sim 86 %$	$< - 13.7$	$< 2.3$	$40 (IL < 2.3 dB & MC < - 11.5 dB)$
Silicon metasurface [25]	${TM}_{0} - to - {TM}_{1} [E]$	1.6	$\sim 75 %$	$< - 11.8$	$< 1.4$	$40 (IL < 2.3 dB & MC < - 11.5 dB)$
Our work	${TM}_{0} - to - {TM}_{1} [S]$	11.8	97.5	$< - 23$	0.29	$100 (CE > 90 %)$

${TM}_{0} - to - {TM}_{1}$	$L_{1}$	$L_{2}$	$L_{3}$	$L_{4}$	$L_{5}$	$W$	$W_{1}$	$W_{2}$	$W_{3}$	$W_{4}$	$H_{1}$	$H_{2}$	$H_{3}$
Value (nm)	3900	1780	4200	1150	770	1400	570	170	490	470	300	300	50

Structure	Function	Length (µm)	CE (%)	MC (dB)	IL (dB)	BW (nm)
MZI [10]	${TE}_{0} - to - {TE}_{1} (E)$	$\sim 60$	-	$< - 20$	$\sim 2$	-
Bragg grating [11]	${TE}_{1} - to - {TE}_{2} (E)$	$\sim 130$	-	$< - 19$	0.2	23 (3 dB BW of CS)
Tilted SWG [12]	${TE}_{0} - to - {TE}_{1} / {TE}_{2} (E)$	5.75/6.736	-	$< - 10$	$< 1$	20 ( $MC < - 10 dB$ )
HRIM [13]	${TE}_{0} - to - {TE}_{1} [S]$	1.5	$\sim 90$	-	0.5	$100 (IL < 0.6 dB)$
Ge/Si pattern [14]	${TE}_{0} - to - {TE}_{1} [S]$	1.55	$> 98$	-	$\sim 0.1$	$100 (CE > 92 %)$
Fully etched slot [21]	${TE}_{0} - to - {TE}_{1} [S]$	5.3	$> 90$	-	$< 0.5$	$100 (CE > 90 %)$
Deeply etched slot [22]	${TE}_{0} - to - {TE}_{1} / {TE}_{2} [S]$	$\sim 24 / \sim 8$	$> 97.6$	$< - 20$	-	$> 100 (MC < - 20 dB & CE > 97 %)$
Deeply etched slot [22]	${TE}_{1} - to - {TE}_{3} / {TE}_{2} [S]$	$\sim 6 / \sim 18$	-	-	-	$> 100 (MC < - 20 dB & CE > 97 %)$
$Si - {Si}_{3} N_{4}$ phase plate [24]	${TE}_{0} - to - {TE}_{1} [S]$	$\sim 1.5$	-	−12.8	1.5	-
$Si - {Si}_{3} N_{4}$ phase plate [24]	${TM}_{0} - to - {TM}_{1} [S]$	$\sim 2$	-	−10.6	2.58	-
Silicon metasurface [25]	${TE}_{0} - to - {TE}_{1} [E]$	1.6	$\sim 86 %$	$< - 13.7$	$< 2.3$	$40 (IL < 2.3 dB & MC < - 11.5 dB)$
Silicon metasurface [25]	${TM}_{0} - to - {TM}_{1} [E]$	1.6	$\sim 75 %$	$< - 11.8$	$< 1.4$	$40 (IL < 2.3 dB & MC < - 11.5 dB)$
Our work	${TM}_{0} - to - {TM}_{1} [S]$	11.8	97.5	$< - 23$	0.29	$100 (CE > 90 %)$

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Journal of the Optical Society of America B