Abstract

A fast, power-efficient electro-optical vector-by-matrix multiplier (VMM) architecture is presented. Careful design of an electrical unit supporting high-speed data transfer enables this architecture to overcome bottlenecks encountered by previous VMM architectures. Based on the proposed architecture, we present an electro-optical digital signal processing (DSP) coprocessor that can achieve a significant speedup of 2–3 orders of magnitude over existing DSP technologies and execute more than 16 teraflops. We show that it is feasible to implement the system using off-the-shelf components, analyze the performance of the architecture with respect to primitive DSP operations, and detail the use of the new architecture for several DSP applications.

© 2009 Optical Society of America

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2008 (2)

J. Dubois, D. Ginhac, M. Paindavoine, and B. Heyrman, “A 10,000 fps CMOS sensor with massively parallel image processing,” IEEE J. Solid-State Circuits 43, 706-717 (2008).
[CrossRef]

M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
[CrossRef]

2007 (5)

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

J. Kim, I. Verbauwhede, and M. F. Chang, “Design of an interconnect architecture and signaling technology for parallelism in communication,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15, 881-894 (2007).
[CrossRef]

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, “A 5-GHz mesh interconnect for a teraflops processor,” Nat. Phys. 27, 51-61 (2007).

N. T. Shaked, S. Messika, S. Dolev, and J. Rosen, “Optical solution for bounded NP-complete problems,” Appl. Opt. 46, 711-724 (2007).
[CrossRef] [PubMed]

N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
[CrossRef]

2005 (1)

A. El Gamal and H. Eltoukhy, “CMOS image sensors,” IEEE Circuits Devices Mag. 21, 6-20 (2005).
[CrossRef]

2004 (2)

I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, and B. J. Hosticka, “A single chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems,” IEEE J. Solid-State Circuits 39, 629-635 (2004).
[CrossRef]

A. Mambu, J. M. Bussat, M. West, B. C. Seller, M. Watanabe, and A. W. Kay, “An ultrahigh-speed one-dimensional detector for use in synchrotron radiation spectroscopy: first photoemission results,” J. Electron Spectrosc. Relat. Phenom. 137, 691-697 (2004).
[CrossRef]

2002 (1)

B. Razavi, “Prospects of CMOS technology for high-speed optical communication circuits,” IEEE J. Solid-State Circuits 37, 1135-1145 (2002).
[CrossRef]

2001 (1)

F. Mederer, R. Jager, H. J. Unold, R. Michalzik, P. Schnitzer, D. Wiedenmann, and K. Ebeling, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13, 1032-1034 (2001).
[CrossRef]

1987 (1)

T. H. Wood, E. C. Carr, C. A. Burrus, J. E. Henry, A. C. Gossard, and J. H. English, “High-speed 2×2 electrically driven spatial light modulator made with GaAs/AlGaAs multiple quantum wells (MQWs),” Electron. Lett. 23, 916-917 (1987).
[CrossRef]

1983 (1)

1982 (1)

1979 (1)

Adams, J.

J. Wolf and J. Adams, 2005 Packaging Roadmap Overview (The International Electronics Manufacturing Initiative, INEMI, 2005).

Agrawal, A.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

Anderson, D.

M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
[CrossRef]

Andruczyk, D.

M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
[CrossRef]

Asgarifar, S.

M. H. Zarifi, J. Frounchi, S. Asgarifar, M. B. Nia, and F. A. Dehkhoda, “High speed low power analog to digital converter for biomedical application,” in Proceedings of Canadian Conference on Electrical and Computer Engineering (IEEE Canada, 2008), pp. 1269-1272.
[CrossRef]

Assaf, S.

A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

Athale, R. A.

Awwal, A. A. S.

M. A. Karim and A. A. S. Awwal, Optical Computing: An Introduction (Wiley, 1992).

Bao, L.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

Barhen, J.

J. Barhen and N. Imam, “Sensor data processing for tracking underwater threats using terascale optical core devices,” in Harbor Protection Through Data Fusion Technologies, E.Shahbazian, G.Rogova, and M.J.DeWeert, eds. (Springer, 2009), pp. 267-282.
[CrossRef]

Bier, J.

J. Bier, Buyers Guide to DSP Processors, 2005 ed. (Berkeley Design Technology, 2006).

Blacksell, M.

M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
[CrossRef]

Blackwell, B. D.

M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
[CrossRef]

Borkar, N.

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, “A 5-GHz mesh interconnect for a teraflops processor,” Nat. Phys. 27, 51-61 (2007).

Borkar, S.

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, “A 5-GHz mesh interconnect for a teraflops processor,” Nat. Phys. 27, 51-61 (2007).

Brockherde, W.

I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, and B. J. Hosticka, “A single chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems,” IEEE J. Solid-State Circuits 39, 629-635 (2004).
[CrossRef]

Brown, J.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

Burrus, C. A.

T. H. Wood, E. C. Carr, C. A. Burrus, J. E. Henry, A. C. Gossard, and J. H. English, “High-speed 2×2 electrically driven spatial light modulator made with GaAs/AlGaAs multiple quantum wells (MQWs),” Electron. Lett. 23, 916-917 (1987).
[CrossRef]

Bussat, J. M.

A. Mambu, J. M. Bussat, M. West, B. C. Seller, M. Watanabe, and A. W. Kay, “An ultrahigh-speed one-dimensional detector for use in synchrotron radiation spectroscopy: first photoemission results,” J. Electron Spectrosc. Relat. Phenom. 137, 691-697 (2004).
[CrossRef]

Carlotto, M.

Carr, E. C.

T. H. Wood, E. C. Carr, C. A. Burrus, J. E. Henry, A. C. Gossard, and J. H. English, “High-speed 2×2 electrically driven spatial light modulator made with GaAs/AlGaAs multiple quantum wells (MQWs),” Electron. Lett. 23, 916-917 (1987).
[CrossRef]

Casasent, D.

Chang, M. F.

J. Kim, I. Verbauwhede, and M. F. Chang, “Design of an interconnect architecture and signaling technology for parallelism in communication,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15, 881-894 (2007).
[CrossRef]

Collins, W. C.

Collis, S. M.

M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
[CrossRef]

Cormen, T. H.

T. H. Cormen, C. E. Leiserson, R. L. Rivest, and R. C. Stein, Introduction to Algorithms, 2nd ed. (MIT Press, 2001).

Debnath, C.

P. N. Singh, A. Kumar, C. Debnath, and R. Malik, “20 mW, 125 Msps, 10 bit pipelined ADC in 65 nm standard digital CMOS process,” in Proceedings of the IEEE Custom Integrated Circuits Conference (IEEE, 2007), pp. 189-192.

Dehkhoda, F. A.

M. H. Zarifi, J. Frounchi, S. Asgarifar, M. B. Nia, and F. A. Dehkhoda, “High speed low power analog to digital converter for biomedical application,” in Proceedings of Canadian Conference on Electrical and Computer Engineering (IEEE Canada, 2008), pp. 1269-1272.
[CrossRef]

Dolev, S.

N. T. Shaked, S. Messika, S. Dolev, and J. Rosen, “Optical solution for bounded NP-complete problems,” Appl. Opt. 46, 711-724 (2007).
[CrossRef] [PubMed]

N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
[CrossRef]

S. Dolev and H. Fitoussi, “The traveling beams optical solutions for bounded NP-complete problems,” in Proceedings of the Fourth International Conference on Fun with Algorithms (FUN2007), LNCS 4475 (Springer LNCS, 2007), pp. 120-134.

S. Dolev and Y. Nir, “Optical implementation of bounded non-deterministic Turing machines,” U.S. Patent No. 7, 130,093 B2, October 31, 2006.

Dubois, J.

J. Dubois, D. Ginhac, M. Paindavoine, and B. Heyrman, “A 10,000 fps CMOS sensor with massively parallel image processing,” IEEE J. Solid-State Circuits 43, 706-717 (2008).
[CrossRef]

Ebeling, K.

F. Mederer, R. Jager, H. J. Unold, R. Michalzik, P. Schnitzer, D. Wiedenmann, and K. Ebeling, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13, 1032-1034 (2001).
[CrossRef]

Edwards, B.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

Eisenbach, S.

S. Eisenbach, “Optical signal processing practical implementation and applications,” Lenslet Marketing Presentation (Lenslet, 2003). http://www.acreo.se/upload/Publications/Proceedings/OE03/LENSLET-OE2003.pdf.

El Gamal, A.

A. El Gamal and H. Eltoukhy, “CMOS image sensors,” IEEE Circuits Devices Mag. 21, 6-20 (2005).
[CrossRef]

Eltoukhy, H.

A. El Gamal and H. Eltoukhy, “CMOS image sensors,” IEEE Circuits Devices Mag. 21, 6-20 (2005).
[CrossRef]

English, J. H.

T. H. Wood, E. C. Carr, C. A. Burrus, J. E. Henry, A. C. Gossard, and J. H. English, “High-speed 2×2 electrically driven spatial light modulator made with GaAs/AlGaAs multiple quantum wells (MQWs),” Electron. Lett. 23, 916-917 (1987).
[CrossRef]

Feitelson, D. G.

D. G. Feitelson, Optical Computing: A Survey for Computer Scientists (MIT Press, 1988).

Fitoussi, H.

S. Dolev and H. Fitoussi, “The traveling beams optical solutions for bounded NP-complete problems,” in Proceedings of the Fourth International Conference on Fun with Algorithms (FUN2007), LNCS 4475 (Springer LNCS, 2007), pp. 120-134.

Frounchi, J.

M. H. Zarifi, J. Frounchi, S. Asgarifar, M. B. Nia, and F. A. Dehkhoda, “High speed low power analog to digital converter for biomedical application,” in Proceedings of Canadian Conference on Electrical and Computer Engineering (IEEE Canada, 2008), pp. 1269-1272.
[CrossRef]

Gerbrands, J. J.

I. T. Young, J. J. Gerbrands, and L. J. van Vliet, Fundamentals of Image Processing (Delft University of Technology, 2005).

Ginhac, D.

J. Dubois, D. Ginhac, M. Paindavoine, and B. Heyrman, “A 10,000 fps CMOS sensor with massively parallel image processing,” IEEE J. Solid-State Circuits 43, 706-717 (2008).
[CrossRef]

Goodman, J. W.

J. W. Goodman, Introduction to Fourier Optics (McGraw-Hill, 1996).

Goren, A.

A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

Gossard, A. C.

T. H. Wood, E. C. Carr, C. A. Burrus, J. E. Henry, A. C. Gossard, and J. H. English, “High-speed 2×2 electrically driven spatial light modulator made with GaAs/AlGaAs multiple quantum wells (MQWs),” Electron. Lett. 23, 916-917 (1987).
[CrossRef]

Griffin, P.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

Gschwind, M.

M. Gschwind, “Chip multiprocessing and the cell broadband engine,” IBM Research Report RC2931 (IBM, 2006).

Hall, D. N. B.

K. W. Hodapp and D. N. B. Hall, “Introduction to detectors: possible status in 2010-2020,” in Proceedings of the International Astronomical Union (Cambridge Univ. Press, 2005), Vol. 1, pp. 40-51.
[CrossRef]

Hashimoto, Y.

T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

Hatakeyama, I.

T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

Hefetz, Y.

A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

Hehemann, I.

I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, and B. J. Hosticka, “A single chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems,” IEEE J. Solid-State Circuits 39, 629-635 (2004).
[CrossRef]

Henry, J. E.

T. H. Wood, E. C. Carr, C. A. Burrus, J. E. Henry, A. C. Gossard, and J. H. English, “High-speed 2×2 electrically driven spatial light modulator made with GaAs/AlGaAs multiple quantum wells (MQWs),” Electron. Lett. 23, 916-917 (1987).
[CrossRef]

Heyrman, B.

J. Dubois, D. Ginhac, M. Paindavoine, and B. Heyrman, “A 10,000 fps CMOS sensor with massively parallel image processing,” IEEE J. Solid-State Circuits 43, 706-717 (2008).
[CrossRef]

Hino, T.

T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

Hodapp, K. W.

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I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, and B. J. Hosticka, “A single chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems,” IEEE J. Solid-State Circuits 39, 629-635 (2004).
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Hosticka, B. J.

I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, and B. J. Hosticka, “A single chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems,” IEEE J. Solid-State Circuits 39, 629-635 (2004).
[CrossRef]

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[CrossRef]

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[CrossRef]

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M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
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I. Hehemann, W. Brockherde, H. Hofmann, A. Kemna, and B. J. Hosticka, “A single chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems,” IEEE J. Solid-State Circuits 39, 629-635 (2004).
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T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

Kuribayashi, R.

T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

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A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

Malik, R.

P. N. Singh, A. Kumar, C. Debnath, and R. Malik, “20 mW, 125 Msps, 10 bit pipelined ADC in 65 nm standard digital CMOS process,” in Proceedings of the IEEE Custom Integrated Circuits Conference (IEEE, 2007), pp. 189-192.

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A. Mambu, J. M. Bussat, M. West, B. C. Seller, M. Watanabe, and A. W. Kay, “An ultrahigh-speed one-dimensional detector for use in synchrotron radiation spectroscopy: first photoemission results,” J. Electron Spectrosc. Relat. Phenom. 137, 691-697 (2004).
[CrossRef]

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N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
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Miao, C.

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

Michalzik, R.

F. Mederer, R. Jager, H. J. Unold, R. Michalzik, P. Schnitzer, D. Wiedenmann, and K. Ebeling, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13, 1032-1034 (2001).
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A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

Nia, M. B.

M. H. Zarifi, J. Frounchi, S. Asgarifar, M. B. Nia, and F. A. Dehkhoda, “High speed low power analog to digital converter for biomedical application,” in Proceedings of Canadian Conference on Electrical and Computer Engineering (IEEE Canada, 2008), pp. 1269-1272.
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T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

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Rairigh, D.

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D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

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T. H. Cormen, C. E. Leiserson, R. L. Rivest, and R. C. Stein, Introduction to Algorithms, 2nd ed. (MIT Press, 2001).

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N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
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A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

Sasaki, J.

T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

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V. Oppenheim and R. W. Schafer, Discrete Time Signal Processing, 2nd ed. (Prentice Hall, 1999).

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F. Mederer, R. Jager, H. J. Unold, R. Michalzik, P. Schnitzer, D. Wiedenmann, and K. Ebeling, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13, 1032-1034 (2001).
[CrossRef]

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A. Mambu, J. M. Bussat, M. West, B. C. Seller, M. Watanabe, and A. W. Kay, “An ultrahigh-speed one-dimensional detector for use in synchrotron radiation spectroscopy: first photoemission results,” J. Electron Spectrosc. Relat. Phenom. 137, 691-697 (2004).
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A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

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G. G. Shahidi, “Evolution of CMOS technology at 32 nm and beyond,” in Proceedings of the IEEE Custom Integrated Circuits Conference (IEEE, 2007), pp. 413-416.

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N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
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N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
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Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, “A 5-GHz mesh interconnect for a teraflops processor,” Nat. Phys. 27, 51-61 (2007).

Singh, P. N.

P. N. Singh, A. Kumar, C. Debnath, and R. Malik, “20 mW, 125 Msps, 10 bit pipelined ADC in 65 nm standard digital CMOS process,” in Proceedings of the IEEE Custom Integrated Circuits Conference (IEEE, 2007), pp. 189-192.

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T. H. Cormen, C. E. Leiserson, R. L. Rivest, and R. C. Stein, Introduction to Algorithms, 2nd ed. (MIT Press, 2001).

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Sugimoto, T.

T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

Tabib, T.

N. T. Shaked, T. Tabib, G. Simon, S. Messika, S. Dolev, and J. Rosen, “Optical binary-matrix synthesis for solving bounded NP-complete combinatorial problems,” Opt. Eng. (Bellingham) 46, 108201:1-11 (2007).
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A. Goren, S. Sariel, Y. Levit, S. Assaf, S. Liberman, B. Sender, T. Tzelnick, Y. Hefetz, E. Moses, and V. Machal, “Vector-matrix multiplication,” U.S. Patent No. 2004/0243657 A1, December 2, 2004.

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F. Mederer, R. Jager, H. J. Unold, R. Michalzik, P. Schnitzer, D. Wiedenmann, and K. Ebeling, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13, 1032-1034 (2001).
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T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps×12 channel pluggable optical transceiver for high-speed interconnections,” in Proceedings of the IEEE Electronic Components and Technology Conference (IEEE, 2008), pp. 1838-1843.

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I. T. Young, J. J. Gerbrands, and L. J. van Vliet, Fundamentals of Image Processing (Delft University of Technology, 2005).

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Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, “A 5-GHz mesh interconnect for a teraflops processor,” Nat. Phys. 27, 51-61 (2007).

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J. Kim, I. Verbauwhede, and M. F. Chang, “Design of an interconnect architecture and signaling technology for parallelism in communication,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15, 881-894 (2007).
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M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell, D. Andruczyk, and B. James, “Imaging photomultiplier array with integrated amplifiers and high-speed USB interface,” Rev. Sci. Instrum. 79, 10F506:1-4 (2008).
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D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. Miao, J. Brown, and A. Agrawal, “On-chip interconnection architecture of the tilera processor,” Nat. Phys. 27, 15-31 (2007).

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A. Mambu, J. M. Bussat, M. West, B. C. Seller, M. Watanabe, and A. W. Kay, “An ultrahigh-speed one-dimensional detector for use in synchrotron radiation spectroscopy: first photoemission results,” J. Electron Spectrosc. Relat. Phenom. 137, 691-697 (2004).
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F. Mederer, R. Jager, H. J. Unold, R. Michalzik, P. Schnitzer, D. Wiedenmann, and K. Ebeling, “3-Gb/s data transmission with GaAs VCSELs over PCB integrated polymer waveguides,” IEEE Photon. Technol. Lett. 13, 1032-1034 (2001).
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M. H. Zarifi, J. Frounchi, S. Asgarifar, M. B. Nia, and F. A. Dehkhoda, “High speed low power analog to digital converter for biomedical application,” in Proceedings of Canadian Conference on Electrical and Computer Engineering (IEEE Canada, 2008), pp. 1269-1272.
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J. Kim, I. Verbauwhede, and M. F. Chang, “Design of an interconnect architecture and signaling technology for parallelism in communication,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15, 881-894 (2007).
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[CrossRef]

“125 Msps14-bit wideband ADC,” Linear Technology, http://www.linear.com/.

T. H. Cormen, C. E. Leiserson, R. L. Rivest, and R. C. Stein, Introduction to Algorithms, 2nd ed. (MIT Press, 2001).

“Basic local alignment search tool (BLAST),” http://www.ncbi.nlm.nih.gov/blast/Blast.cgi.

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Figures (7)

Fig. 1
Fig. 1

Electro-optical computing system.

Fig. 2
Fig. 2

VMM architecture.

Fig. 3
Fig. 3

VMM optical unit.

Fig. 4
Fig. 4

VMM electrical driver.

Fig. 5
Fig. 5

A 1 × 256 SLM electrical driver.

Fig. 6
Fig. 6

ALU chip.

Fig. 7
Fig. 7

Interface board.

Equations (1)

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[ A 0 0 B ] × [ C D ] = [ A × C B × D ] .

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