Abstract

Optical and electronic means have been devised and tested for reversible counting of fringes from a corner-cube or Michelson interferometer. Counting rates of 1000/sec have been achieved but do not represent the attainable limit.

© 1953 Optical Society of America

Full Article  |  PDF Article

References

  • View by:
  • |
  • |
  • |

  1. E. R. Peck, J. Opt. Soc. Am. 38, No. 1, 66 (1948).
    [Crossref] [PubMed]
  2. E. R. Peck, J. Opt. Soc. Am. 38, 1015–1024 (1948).
    [Crossref] [PubMed]
  3. K. H. Barney, “A Binary Quantizer,” M.S. thesis, Northwestern Technological Institute, 1949.
  4. Elmore and Sands, Electronics (McGraw-Hill Book Company, Inc., New York, 1949), pp. 99–103.

1948 (2)

Barney, K. H.

K. H. Barney, “A Binary Quantizer,” M.S. thesis, Northwestern Technological Institute, 1949.

Elmore,

Elmore and Sands, Electronics (McGraw-Hill Book Company, Inc., New York, 1949), pp. 99–103.

Peck, E. R.

Sands,

Elmore and Sands, Electronics (McGraw-Hill Book Company, Inc., New York, 1949), pp. 99–103.

J. Opt. Soc. Am. (2)

Other (2)

K. H. Barney, “A Binary Quantizer,” M.S. thesis, Northwestern Technological Institute, 1949.

Elmore and Sands, Electronics (McGraw-Hill Book Company, Inc., New York, 1949), pp. 99–103.

Cited By

OSA participates in Crossref's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.

Alert me when this article is cited.


Figures (9)

Fig. 1
Fig. 1

The two photocell currents having a 90° phase difference, which permit reversible counting.

Fig. 2
Fig. 2

An arrangement giving two fringe patterns, in general out of phase, from one interferometer.

Fig. 3
Fig. 3

Allowed counting intervals.

Fig. 4
Fig. 4

Block diagram of a reversible binary counter.

Fig. 5
Fig. 5

Block diagram of the trigger and gating circuits of the reversible fringe counter.

Fig. 6
Fig. 6

Operation of the Schmitt trigger circuit.

Fig. 7
Fig. 7

Setting of Schmitt threshold levels.

Fig. 8
Fig. 8

Complete schematic of the trigger and gating circuits.

Fig. 9
Fig. 9

Schematic of a typical stage of the binary counter.