Abstract

High-performance computing systems and datacenters will interconnect hundreds to thousands of heterogeneous general purpose or specialized cores in the future. As the number of network end-point sockets scales exponentially, the underlying communication fabric must deliver high bandwidth with low power and reduced switching complexity. While high-radix routers enable smaller diameter networks, the penalty is in increased switching complexity and router power. In this paper, we propose SPRINT (scalable photonic reconfigurable interconnect), which can scale to a large number of cores using photonic switching implemented with silicon micro-ring resonators (MRRs). MRRs are low power, high bandwidth photonic switching devices that can be arranged to function similarly to a high-radix router with reduced complexity and power. We will first show the design of a 64 core cluster using optical interconnects and electrical packet switching. To build scalable switching crossconnects, we investigate the design of 256-, 512- and 1024-socket versions of SPRINT connected to function as passive arrayed-waveguide gratings. Our proposed switching crossconnect with single and dual micro-rings minimizes the hop count to 4 for a 1024 core network while reducing the power dissipation, increasing the bandwidth and reducing the switching complexity.

© 2012 OSA

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  1. D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, no. 7, pp. 1166–1185, July2009.
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  2. A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
    [CrossRef]
  3. R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
    [CrossRef]
  4. J. Kim, W. J. Dally, and D. Abts, “Flattened butterfly: Cost-efficient topology for high-radix networks,” in Proc. of the 34th Annu. Int. Symp. on Computer Architecture (ISCA), June 2007, pp. 126–137.
  5. J. Kim, W. Dally, S. Scott, and D. Abts, “Technology-driven, highly-scalable dragonfly topology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 77–88.
  6. S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix Clos network,” in 33rd Annu. Int. Symp. on Computer Architecture (ISCA), 2006, pp. 16–28.
  7. N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.
  8. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.
  9. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.
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  20. J. Balfour and W. J. Dally, “Design tradeoffs for tiled CMP on-chip networks,” in Proc. of the 20th ACM Int. Conf. on Supercomputing (ICS), Cairns, Australia, June 28–30, 2006, pp. 187–198.
  21. R. W. Morris and A. K. Kodi, “Power-efficient and high-performance multi-level hybrid nanophotonic interconnect for multicores,” in Proc. of the 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2010, pp. 207–214.
  22. L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
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    [CrossRef]
  25. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Fransisco, USA, 2004.
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    [CrossRef]

2010 (2)

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

2009 (1)

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, no. 7, pp. 1166–1185, July2009.
[CrossRef]

2008 (4)

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, pp. 1246–1260, Sept.2008.
[CrossRef]

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

2007 (2)

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, July2007.
[CrossRef]

A. Kodi and A. Louri, “A system simulation methodology of optical interconnects for high-performance computing systems,” J. Opt. Netw., vol. 6, no. 12, pp. 1282–1300, Dec.2007.
[CrossRef]

2006 (1)

C. Gunn, “CMOS photonics for high speed interconnects,” IEEE Photon. Technol. Lett., vol. 26, pp. 58–66, 2006.

2005 (1)

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

Abts, D.

J. Kim, W. J. Dally, and D. Abts, “Flattened butterfly: Cost-efficient topology for high-radix networks,” in Proc. of the 34th Annu. Int. Symp. on Computer Architecture (ISCA), June 2007, pp. 126–137.

S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix Clos network,” in 33rd Annu. Int. Symp. on Computer Architecture (ISCA), 2006, pp. 16–28.

J. Kim, W. Dally, S. Scott, and D. Abts, “Technology-driven, highly-scalable dragonfly topology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 77–88.

Ahn, J. H.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Akella, V.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

Albonesi, D.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

Amirtharajah, R.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Andersen, D. G.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Apsel, A.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

Asanovic, K.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Balfour, J.

J. Balfour and W. J. Dally, “Design tradeoffs for tiled CMP on-chip networks,” in Proc. of the 20th ACM Int. Conf. on Supercomputing (ICS), Cairns, Australia, June 28–30, 2006, pp. 187–198.

Ballato, J.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

Batten, C.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Bazzaz, H. H.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Beausoleil, R.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Beausoleil, R. G.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

Benner, A. F.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

Bergman, K.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, pp. 1246–1260, Sept.2008.
[CrossRef]

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, July2007.
[CrossRef]

Binker, N.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, pp. 1246–1260, Sept.2008.
[CrossRef]

Choudhary, A.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

Dally, W.

J. Kim, W. Dally, S. Scott, and D. Abts, “Technology-driven, highly-scalable dragonfly topology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 77–88.

Dally, W. J.

J. Balfour and W. J. Dally, “Design tradeoffs for tiled CMP on-chip networks,” in Proc. of the 20th ACM Int. Conf. on Supercomputing (ICS), Cairns, Australia, June 28–30, 2006, pp. 187–198.

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Fransisco, USA, 2004.

J. Kim, W. J. Dally, and D. Abts, “Flattened butterfly: Cost-efficient topology for high-radix networks,” in Proc. of the 34th Annu. Int. Symp. on Computer Architecture (ISCA), June 2007, pp. 126–137.

S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix Clos network,” in 33rd Annu. Int. Symp. on Computer Architecture (ISCA), 2006, pp. 16–28.

Davis, A.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Ding, D.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Djordjevic, S.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Dokania, R.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

Fainman, Y.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Farrington, N.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Fiorentino, M.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Gunn, C.

C. Gunn, “CMOS photonics for high speed interconnects,” IEEE Photon. Technol. Lett., vol. 26, pp. 58–66, 2006.

Ho, R.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

Holzwarth, C.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Hoyt, J.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Ignatowski, M.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

Joshi, A.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Jouppi, N.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Kaminsky, M.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Kartner, F.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Kash, J. A.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

Khilo, A.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Kim, J.

J. Kim, W. J. Dally, and D. Abts, “Flattened butterfly: Cost-efficient topology for high-radix networks,” in Proc. of the 34th Annu. Int. Symp. on Computer Architecture (ISCA), June 2007, pp. 126–137.

S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix Clos network,” in 33rd Annu. Int. Symp. on Computer Architecture (ISCA), 2006, pp. 16–28.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

J. Kim, W. Dally, S. Scott, and D. Abts, “Technology-driven, highly-scalable dragonfly topology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 77–88.

Kim, S.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

Kirman, M.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

Kirman, N.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

Kodi, A.

Kodi, A. K.

R. W. Morris and A. K. Kodi, “Power-efficient and high-performance multi-level hybrid nanophotonic interconnect for multicores,” in Proc. of the 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2010, pp. 207–214.

Koka, P.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

Kozuch, M.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Krishnamoorthy, A. V.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

Kuchta, D. M.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

Kuekes, P. J.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

Kumar, P.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

Li, H.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Lin, Y.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

Louri, A.

Malik, S.

H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, “Orion: A power-performance simulator for interconnection networks,” in Proc. of the 35th Annu. ACM/IEEE Int. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 18–22, 2002, pp. 294–305.

Martinez, J.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

McCracken, M. O.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

McLaren, M.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Mejia, P.

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

Memik, G.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

Miller, D. A. B.

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, no. 7, pp. 1166–1185, July2009.
[CrossRef]

Monchiero, M.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Morris, R. W.

R. W. Morris and A. K. Kodi, “Power-efficient and high-performance multi-level hybrid nanophotonic interconnect for multicores,” in Proc. of the 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2010, pp. 207–214.

Moss, B.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Ng, T. E.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Nordin, G. P.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

O’Connor, I.

I. O’Connor, “Optical solutions for system-level interconnect,” in Proc. of the 2004 Int. Workshop on System Level Interconnect Prediction, ACM, 2004, pp. 79–88.

Orcutt, J.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Pan, Y.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

Papagiannaki, K.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Papen, G.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Peh, L. S.

H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, “Orion: A power-performance simulator for interconnection networks,” in Proc. of the 35th Annu. ACM/IEEE Int. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 18–22, 2002, pp. 294–305.

Popovic, M.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Porter, G.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Proietti, R.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

Radhakrishnan, S.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Rahmanian, N.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

Ram, R.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Ramachandran, K.

A. Singla, A. Singh, K. Ramachandran, L. Xu, and Y. Zhang, “Proteus: a topology malleable data center network,” in Proc. of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks (Hotnets), 2010.

Ritter, M. B.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

Ryan, M.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Schreiber, R.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Schwetman, H.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

Scott, S.

S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix Clos network,” in 33rd Annu. Int. Symp. on Computer Architecture (ISCA), 2006, pp. 16–28.

J. Kim, W. Dally, S. Scott, and D. Abts, “Technology-driven, highly-scalable dragonfly topology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 77–88.

Shacham, A.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, pp. 1246–1260, Sept.2008.
[CrossRef]

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, July2007.
[CrossRef]

Singh, A.

A. Singla, A. Singh, K. Ramachandran, L. Xu, and Y. Zhang, “Proteus: a topology malleable data center network,” in Proc. of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks (Hotnets), 2010.

Singla, A.

A. Singla, A. Singh, K. Ramachandran, L. Xu, and Y. Zhang, “Proteus: a topology malleable data center network,” in Proc. of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks (Hotnets), 2010.

Smith, D.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

Smith, H.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Snider, G. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

Stojanovi, V.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

Subramanya, V.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Topping, C.

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

Towles, B.

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Fransisco, USA, 2004.

Vahdat, A.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

Vantrease, D.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

Wang, G.

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

Wang, H. S.

H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, “Orion: A power-performance simulator for interconnection networks,” in Proc. of the 35th Annu. ACM/IEEE Int. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 18–22, 2002, pp. 294–305.

Wang, S.-Y.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

Watkins, M.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

Williams, R. S.

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

Xu, L.

A. Singla, A. Singh, K. Ramachandran, L. Xu, and Y. Zhang, “Proteus: a topology malleable data center network,” in Proc. of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks (Hotnets), 2010.

Ye, X.

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

Yin, Y.

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

Yoo, S.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Yoo, S. J. B.

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

Zhang, Y.

A. Singla, A. Singh, K. Ramachandran, L. Xu, and Y. Zhang, “Proteus: a topology malleable data center network,” in Proc. of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks (Hotnets), 2010.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

Zheng, X.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

Zhou, L.

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Zhu, X.

H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, “Orion: A power-performance simulator for interconnection networks,” in Proc. of the 35th Annu. ACM/IEEE Int. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 18–22, 2002, pp. 294–305.

Appl. Phys. A (1)

L. Zhou, S. Djordjevic, R. Proietti, D. Ding, S. Yoo, R. Amirtharajah, and V. Akella, “Design and evaluation of an arbitration-free passive optical crossbar for on-chip interconnection networks,” Appl. Phys. A, vol. 95, no. 10, pp. 1111–1118, Oct.2008.
[CrossRef]

Comput. Commun. Rev. (2)

G. Wang, D. G. Andersen, M. Kaminsky, K. Papagiannaki, T. E. Ng, M. Kozuch, and M. Ryan, “c-Through: Part-time optics in data centers,” Comput. Commun. Rev., vol. 41, pp. 327–338, Aug.2010.

N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz, V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios: A hybrid electrical/optical switch architecture for modular data centers,” Comput. Commun. Rev., vol. 41, pp. 339–350, Aug.2010.

IBM J. Res. Dev. (1)

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev., vol. 49, no. 4/5, pp. 755–775, Sept.2005.
[CrossRef]

IEEE Micro (1)

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, July2007.
[CrossRef]

IEEE Photon. Technol. Lett. (1)

C. Gunn, “CMOS photonics for high speed interconnects,” IEEE Photon. Technol. Lett., vol. 26, pp. 58–66, 2006.

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, pp. 1246–1260, Sept.2008.
[CrossRef]

J. Lightwave Technol. (1)

Y. Lin, N. Rahmanian, S. Kim, G. P. Nordin, C. Topping, D. Smith, and J. Ballato, “Ultracompact AWG using air-trench bends with perfluorocyclobutyl polymer waveguides,” J. Lightwave Technol., no. 17, pp. 3062–3070, Sept.2008.
[CrossRef]

J. Opt. Netw. (1)

Proc. IEEE (2)

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, no. 7, pp. 1166–1185, July2009.
[CrossRef]

R. G. Beausoleil, P. J. Kuekes, G. S. Snider, S.-Y. Wang, and R. S. Williams, “Nanoelectronic and nanophotonic interconnect,” Proc. IEEE, vol. 96, no. 2, pp. 230–247, Feb.2008.
[CrossRef]

Other (15)

J. Kim, W. J. Dally, and D. Abts, “Flattened butterfly: Cost-efficient topology for high-radix networks,” in Proc. of the 34th Annu. Int. Symp. on Computer Architecture (ISCA), June 2007, pp. 126–137.

J. Kim, W. Dally, S. Scott, and D. Abts, “Technology-driven, highly-scalable dragonfly topology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 77–88.

S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix Clos network,” in 33rd Annu. Int. Symp. on Computer Architecture (ISCA), 2006, pp. 16–28.

N. Kirman, M. Kirman, R. Dokania, J. Martinez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proc. of the 39th Int. Symp. on Microarchitecture, Dec. 2006.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovi, and K. Asanovic, “Building manycore processor-to-dram networks with monolithic silicon photonics,” in Proc. of the 16th Annu. Symp. on High-Performance Interconnects, Aug. 27–28, 2008.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binker, R. Beausoleil, and J. H. Ahn, “Corona: System implications of emerging nanophotonic technology,” in Proc. of the 35th Annu. Int. Symp. on Computer Architecture (ISCA), June 2008, pp. 153–164.

X. Ye, Y. Yin, S. J. B. Yoo, P. Mejia, R. Proietti, and V. Akella, “DOS: A scalable optical switch for datacenters,” in Proc. of the 6th ACM/IEEE Symp. on Architectures for Networking and Communications Systems (ANCS), 2010.

A. Singla, A. Singh, K. Ramachandran, L. Xu, and Y. Zhang, “Proteus: a topology malleable data center network,” in Proc. of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks (Hotnets), 2010.

Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” in Proc. of the 36th Annu. Int. Symp. on Computer Architecture (ISCA), 2009.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, “Silicon-photonic network architectures for scalable, power-efficient multi-chip systems,” in Proc. of the 37th Annu. Int. Symp. on Computer Architecture (ISCA), 2010.

J. Balfour and W. J. Dally, “Design tradeoffs for tiled CMP on-chip networks,” in Proc. of the 20th ACM Int. Conf. on Supercomputing (ICS), Cairns, Australia, June 28–30, 2006, pp. 187–198.

R. W. Morris and A. K. Kodi, “Power-efficient and high-performance multi-level hybrid nanophotonic interconnect for multicores,” in Proc. of the 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2010, pp. 207–214.

I. O’Connor, “Optical solutions for system-level interconnect,” in Proc. of the 2004 Int. Workshop on System Level Interconnect Prediction, ACM, 2004, pp. 79–88.

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Fransisco, USA, 2004.

H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, “Orion: A power-performance simulator for interconnection networks,” in Proc. of the 35th Annu. ACM/IEEE Int. Symp. on Microarchitecture, Istanbul, Turkey, Nov. 18–22, 2002, pp. 294–305.

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Figures (6)

Fig. 1
Fig. 1

(Color online) A 64 core cluster with Cx = 4,Cy = 4,Dx = 0, and Dy = 0; Sl(x,y) with 0x3 and 0y3. The top inset shows the core concentration, the left inset shows the AWG configuration and the right inset shows the microarchitecture.

Fig. 2
Fig. 2

(Color online) SPRINT design configurations: (a) 256 cores, (b) 512 cores, (c) 1024 cores. Note: not all connections are shown for clarity.

Fig. 3
Fig. 3

4-input, 4-output, 64-wavelength AWG functionality.

Fig. 4
Fig. 4

(Color online) Proposed four-input 64-wavelength AWG implementations using MRRs with (a) single ring resonators and (b) double ring resonators. (c) A double MRR switching two optical light beams.

Fig. 5
Fig. 5

(Color online) Power evaluation. (a) 256 core mesh network compared with SPRINT connected together by 8 (SPRINT-8) and 16 (SPRINT-16) AWG switches; (b) comparison of mesh, cmesh and SPRINT topologies for 256, 512 and 1024 cores for uniform traffic and (c) various versions of SPRINT (256, 512 and 1024) evaluated with 4, 8 and 16 wavelengths on different traffic traces (U = uniform, B = Butterfly, C = Complement, T = Tornado).

Fig. 6
Fig. 6

(Color online) Power evaluation. (a) 256 core mesh network compared with SPRINT connected together by 8 (SPRINT-8) and 16 (SPRINT-16) AWG switches; (b) comparison of mesh, cmesh and SPRINT topologies for 256, 512 and 1024 cores for uniform traffic and (c) various versions of SPRINT (256, 512 and 1024) evaluated with 4, 8 and 16 wavelengths on different traffic traces (U = uniform, B = Butterfly, C = Complement, T = Tornado).

Tables (2)

Tables Icon

Table I Comparison Between the Single and Double Micro-ring AWG Designs

Tables Icon

Table II Optical Component Link Losses