Abstract

Speculative transmission has been proposed to overcome the high latency of setting up end-to-end paths through photonic networks for computer systems. However, speculative transmission has implications for the energy efficiency of the network, in particular, control circuits are more complex and power hungry and failed speculative transmissions must be repeated. Moreover, in future chip multiprocessors (CMPs) with integrated photonic network end points, a large proportion of the additional energy will be dissipated on the CMP. This paper compares the energy characteristics of scheduled and speculative chip-to-chip networks for shared memory computer systems on the scale of a rack. For this comparison, we use a novel speculative control plane which reduces energy consumption by eliminating duplicate packets from the allocation process. In addition, we consider photonic power gating to reduce processor chip energy dissipation and the energy impact of the choice between semiconductor optical amplifier and ring resonator switching technologies. We model photonic network elements using values from the published literature as well as determine the power consumption of the allocator and network adapter circuits, implemented in a commercial low leakage 45 nm CMOS process. The power dissipated on the CMP using speculative networks is shown to be roughly double that of scheduled networks at saturation load and an order of magnitude higher at low loads.

© 2012 OSA

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2011 (3)

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
[CrossRef]

R. S. Tucker, “Green optical communications—Part II: Energy limitations in networks,” IEEE J. Sel. Top. Quantum Electron., vol. 17, no. 2, pp. 245–260, 2011.
[CrossRef]

A. Wonfor, H. Wang, R. Penty, and I. White, “Large port count high-speed optical switch fabric for use within datacenters [Invited],” J. Opt. Commun. Netw., vol. 3, no. 8, pp. A32–A39, Aug.2011.
[CrossRef]

2010 (1)

G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nat. Photonics, vol. 4, no. 8, pp. 518–526, 2010.
[CrossRef]

2009 (3)

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, pp. 1166–1185, 2009.
[CrossRef]

A. W. Poon, X. S. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE, vol. 97, no. 7, pp. 1216–1238, 2009.
[CrossRef]

I. White, A. E. Tin, K. Williams, H. B. Wang, A. Wonfor, and R. Penty, “Scalable optical switches for computing applications,” J. Opt. Netw., vol. 8, no. 2, pp. 215–224, 2009.
[CrossRef]

2008 (5)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, no. 9, pp. 1246–1260, 2008.
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express, vol. 16, no. 20, pp. 15915–15922, 2008.
[CrossRef] [PubMed]

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

I. Iliadis and C. Minkenberg, “Performance of a speculative transmission scheme for scheduling-latency reduction,” IEEE/ACM Trans. Netw., vol. 16, no. 1, pp. 182–195, 2008.
[CrossRef]

B. G. Lee, A. Biberman, D. Po, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photon. Technol. Lett., vol. 20, no. 10, pp. 767–769, 2008.
[CrossRef]

2007 (3)

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, 2007.
[CrossRef]

J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, “A 14 mW 6.25-Gb/s transceiver in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745–2757, 2007.
[CrossRef]

B. G. Lee, B. A. Small, Q. F. Xu, M. Lipson, and K. Bergman, “Characterization of a 4 × 4 Gb/s parallel electronic bus to WDM optical link silicon photonic translator,” IEEE Photon. Technol. Lett., vol. 19, no. 5, pp. 456–458, 2007.
[CrossRef]

2006 (2)

O. Liboiron-Ladouceur, B. A. Small, and K. Bergman, “Physical layer scalability of WDM optical packet interconnection networks,” J. Lightwave Technol., vol. 24, no. 1, pp. 262–270, 2006.
[CrossRef]

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

2003 (1)

1999 (2)

P. Gupta and N. McKeown, “Designing and implementing a fast crossbar scheduler,” IEEE Micro, vol. 19, no. 1, pp. 20–28, 1999.
[CrossRef]

N. McKeown, “The iSLIP scheduling algorithm for input-queued switches,” IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188–201, 1999.
[CrossRef]

Abel, F.

C. Minkenberg, I. Iliadis, and F. Abel, “Low-latency pipelined crossbar arbitration,” in IEEE Global Telecommunications Conf. (GLOBECOM), 2004, vol. 2, pp. 1174–1179.

Almeida, V. R.

Andry, P. S.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

Audzevich, Y.

Y. Audzevich, P. M. Watts, S. Kilmurray, and A. W. Moore, “Efficient photonic coding: A considered revision,” in GreenNets 2011 (SIGCOM workshop), Aug. 2011.

Baks, C. W.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Barker, K. J.

K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

Benner, A.

K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

Bergman, K.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, no. 9, pp. 1246–1260, 2008.
[CrossRef]

B. G. Lee, A. Biberman, D. Po, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photon. Technol. Lett., vol. 20, no. 10, pp. 767–769, 2008.
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express, vol. 16, no. 20, pp. 15915–15922, 2008.
[CrossRef] [PubMed]

B. G. Lee, B. A. Small, Q. F. Xu, M. Lipson, and K. Bergman, “Characterization of a 4 × 4 Gb/s parallel electronic bus to WDM optical link silicon photonic translator,” IEEE Photon. Technol. Lett., vol. 19, no. 5, pp. 456–458, 2007.
[CrossRef]

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, 2007.
[CrossRef]

O. Liboiron-Ladouceur, B. A. Small, and K. Bergman, “Physical layer scalability of WDM optical packet interconnection networks,” J. Lightwave Technol., vol. 24, no. 1, pp. 262–270, 2006.
[CrossRef]

A. Biberman, G. Hendry, J. Chan, H. Wang, K. Bergman, K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “CMOS-compatible scalable photonic switch architecture using 3D-integrated deposited silicon materials for high-performance data center networks,” in Proc. Optical Fiber Communications Conf., Mar. 2011.

Biberman, A.

B. G. Lee, A. Biberman, D. Po, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photon. Technol. Lett., vol. 20, no. 10, pp. 767–769, 2008.
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express, vol. 16, no. 20, pp. 15915–15922, 2008.
[CrossRef] [PubMed]

A. Biberman, G. Hendry, J. Chan, H. Wang, K. Bergman, K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “CMOS-compatible scalable photonic switch architecture using 3D-integrated deposited silicon materials for high-performance data center networks,” in Proc. Optical Fiber Communications Conf., Mar. 2011.

Blem, E.

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, “Dark silicon and the end of multicore scaling,” in Proc. of the 38th Annu. Int. Symp. on Computer Architecture, 2011.

Block, B. A.

M. R. Reshotko, B. A. Block, B. Jin, and P. Chang, “Waveguide coupled Ge-on-oxide photodetectors for integrated optical links,” in 5th IEEE Int. Conf. on Group IV Photonics, 2008, pp. 182–184.

Bour, D. P.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Budd, R. A.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Burger, D.

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, “Dark silicon and the end of multicore scaling,” in Proc. of the 38th Annu. Int. Symp. on Computer Architecture, 2011.

Carloni, L. P.

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, no. 9, pp. 1246–1260, 2008.
[CrossRef]

Chan, J.

A. Biberman, G. Hendry, J. Chan, H. Wang, K. Bergman, K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “CMOS-compatible scalable photonic switch architecture using 3D-integrated deposited silicon materials for high-performance data center networks,” in Proc. Optical Fiber Communications Conf., Mar. 2011.

Chang, P.

M. R. Reshotko, B. A. Block, B. Jin, and P. Chang, “Waveguide coupled Ge-on-oxide photodetectors for integrated optical links,” in 5th IEEE Int. Conf. on Group IV Photonics, 2008, pp. 182–184.

Changku, H.

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
[CrossRef]

Chen, H.

A. W. Poon, X. S. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE, vol. 97, no. 7, pp. 1216–1238, 2009.
[CrossRef]

Chen, L.

Chen, T. W. Y.

T. W. Y. Chen and R. Katz, “Energy efficient Ethernet encodings,” in 33rd IEEE Conf. on Local Computer Networks (LCN), Oct. 2008, pp. 122–129.

Chiniwalla, P.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Cunningham, J. E.

X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

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J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, “A 14 mW 6.25-Gb/s transceiver in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745–2757, 2007.
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K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

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X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

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Li, H.

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
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L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
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L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
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J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
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K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

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N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express, vol. 16, no. 20, pp. 15915–15922, 2008.
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Shin, J. L.

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
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X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

J. E. Cunningham, I. Shubin, X. Zheng, G. Li, H. Thacker, Y. Luo, J. Yao, K. Raj, B. Guenin, T. Pinguet, and A. V. Krishnamoorthy, “Compact, thermally-tuned resonant ring muxes in CMOS with integrated backside pyramidal etch pit,” in Proc. Optical Fiber Communication Conf. (OFC), 2011.

Sirdeshmukh, R.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

Small, B. A.

B. G. Lee, B. A. Small, Q. F. Xu, M. Lipson, and K. Bergman, “Characterization of a 4 × 4 Gb/s parallel electronic bus to WDM optical link silicon photonic translator,” IEEE Photon. Technol. Lett., vol. 19, no. 5, pp. 456–458, 2007.
[CrossRef]

O. Liboiron-Ladouceur, B. A. Small, and K. Bergman, “Physical layer scalability of WDM optical packet interconnection networks,” J. Lightwave Technol., vol. 24, no. 1, pp. 262–270, 2006.
[CrossRef]

Smith, A.

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
[CrossRef]

Sprogis, E. J.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

Sri-Jayantha, S. M.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

St. Amant, R.

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, “Dark silicon and the end of multicore scaling,” in Proc. of the 38th Annu. Int. Symp. on Computer Architecture, 2011.

Stephens, A. M.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

Strong, A.

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
[CrossRef]

Stunkel, C.

K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

Sun, R.

W. N. Ye, R. Sun, J. Michel, L. Eldada, D. Pant, and L. C. Kimerling, “Thermo-optical compensation in high-index-contrast waveguides,” in 5th IEEE Int. Conf. on Group IV Photonics, 2008.

Takayama, K.

Y. Kuwana, S. Takenobu, K. Takayama, S. Yokotsuka, and S. Kodama, “Low loss and highly reliable polymer optical waveguides with perfluorinated dopant-free core,” in Optical Fiber Communication Conf. (OFC), Mar. 2006.

Takenobu, S.

Y. Kuwana, S. Takenobu, K. Takayama, S. Yokotsuka, and S. Kodama, “Low loss and highly reliable polymer optical waveguides with perfluorinated dopant-free core,” in Optical Fiber Communication Conf. (OFC), Mar. 2006.

Tam, K. W.

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
[CrossRef]

Tan, M. R. T.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Tandon, A.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Thacker, H.

X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

J. E. Cunningham, I. Shubin, X. Zheng, G. Li, H. Thacker, Y. Luo, J. Yao, K. Raj, B. Guenin, T. Pinguet, and A. V. Krishnamoorthy, “Compact, thermally-tuned resonant ring muxes in CMOS with integrated backside pyramidal etch pit,” in Proc. Optical Fiber Communication Conf. (OFC), 2011.

Thomson, D. J.

G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nat. Photonics, vol. 4, no. 8, pp. 518–526, 2010.
[CrossRef]

Tin, A. E.

Topol, A. W.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

Trewhella, J. M.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Trott, G. R.

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Tsang, C. K.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

Tucker, R. S.

R. S. Tucker, “Green optical communications—Part II: Energy limitations in networks,” IEEE J. Sel. Top. Quantum Electron., vol. 17, no. 2, pp. 245–260, 2011.
[CrossRef]

Vlasov, U.

U. Vlasov, “Silicon photonics for next generation computing systems,” in European Conf. on Optical Communications (ECOC), 2008.

Walker, P.

K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

Wang, H.

A. Wonfor, H. Wang, R. Penty, and I. White, “Large port count high-speed optical switch fabric for use within datacenters [Invited],” J. Opt. Commun. Netw., vol. 3, no. 8, pp. A32–A39, Aug.2011.
[CrossRef]

N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC),” Opt. Express, vol. 16, no. 20, pp. 15915–15922, 2008.
[CrossRef] [PubMed]

A. Biberman, G. Hendry, J. Chan, H. Wang, K. Bergman, K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “CMOS-compatible scalable photonic switch architecture using 3D-integrated deposited silicon materials for high-performance data center networks,” in Proc. Optical Fiber Communications Conf., Mar. 2011.

Wang, H. B.

Watts, P. M.

Y. Audzevich, P. M. Watts, S. Kilmurray, and A. W. Moore, “Efficient photonic coding: A considered revision,” in GreenNets 2011 (SIGCOM workshop), Aug. 2011.

Webb, B. C.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

White, I.

White, I. H.

I. H. White and R. V. Penty, “Optical interconnects for backplane and chip-to-chip photonics,” in 2nd ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS ’08), 2008.

Williams, K.

Wonfor, A.

Wright, S. L.

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

Xu, F.

A. W. Poon, X. S. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE, vol. 97, no. 7, pp. 1216–1238, 2009.
[CrossRef]

Xu, Q. F.

B. G. Lee, B. A. Small, Q. F. Xu, M. Lipson, and K. Bergman, “Characterization of a 4 × 4 Gb/s parallel electronic bus to WDM optical link silicon photonic translator,” IEEE Photon. Technol. Lett., vol. 19, no. 5, pp. 456–458, 2007.
[CrossRef]

Yao, J.

X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

J. E. Cunningham, I. Shubin, X. Zheng, G. Li, H. Thacker, Y. Luo, J. Yao, K. Raj, B. Guenin, T. Pinguet, and A. V. Krishnamoorthy, “Compact, thermally-tuned resonant ring muxes in CMOS with integrated backside pyramidal etch pit,” in Proc. Optical Fiber Communication Conf. (OFC), 2011.

Ye, W. N.

W. N. Ye, R. Sun, J. Michel, L. Eldada, D. Pant, and L. C. Kimerling, “Thermo-optical compensation in high-index-contrast waveguides,” in 5th IEEE Int. Conf. on Group IV Photonics, 2008.

Yokotsuka, S.

Y. Kuwana, S. Takenobu, K. Takayama, S. Yokotsuka, and S. Kodama, “Low loss and highly reliable polymer optical waveguides with perfluorinated dopant-free core,” in Optical Fiber Communication Conf. (OFC), Mar. 2006.

Zheng, X.

X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

J. E. Cunningham, I. Shubin, X. Zheng, G. Li, H. Thacker, Y. Luo, J. Yao, K. Raj, B. Guenin, T. Pinguet, and A. V. Krishnamoorthy, “Compact, thermally-tuned resonant ring muxes in CMOS with integrated backside pyramidal etch pit,” in Proc. Optical Fiber Communication Conf. (OFC), 2011.

IBM J. Res. Dev. (1)

J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, “Three-dimensional silicon integration,” IBM J. Res. Dev., vol. 52, no. 6, pp. 553–569, 2008.
[CrossRef]

IEEE J. Sel. Top. Quantum Electron. (2)

L. Schares, J. A. Kash, F. E. Doany, C. L. Schow, C. Schuster, D. M. Kuchta, P. K. Pepeljugoski, J. M. Trewhella, C. W. Baks, R. A. John, L. Shan, Y. H. Kwark, R. A. Budd, P. Chiniwalla, F. R. Libsch, J. Rosner, C. K. Tsang, C. S. Patel, J. D. Schaub, R. Dangel, F. Horst, B. J. Offrein, D. Kucharski, D. Guckenberger, S. Hedge, H. Nyikal, C.-K. Lin, A. Tandon, G. R. Trott, M. Nystrom, D. P. Bour, M. R. T. Tan, and D. W. Dolfi, “Terabus: Terabit/second-class card-level optical interconnect technologies,” IEEE J. Sel. Top. Quantum Electron., vol. 12, no. 5, pp. 1032–1044, 2006.
[CrossRef]

R. S. Tucker, “Green optical communications—Part II: Energy limitations in networks,” IEEE J. Sel. Top. Quantum Electron., vol. 17, no. 2, pp. 245–260, 2011.
[CrossRef]

IEEE J. Solid-State Circuits (2)

J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, “A 14 mW 6.25-Gb/s transceiver in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745–2757, 2007.
[CrossRef]

J. L. Shin, H. Dawei, B. Petrick, H. Changku, K. W. Tam, A. Smith, H. Pham, H. Li, T. Johnson, F. Schumacher, A. S. Leon, and A. Strong, “A 40 nm 16-core 128-thread SPARC SoC processor,” IEEE J. Solid-State Circuits, vol. 46, pp. 131–144, 2011.
[CrossRef]

IEEE Micro (2)

A. Shacham and K. Bergman, “Building ultralow-latency interconnection networks using photonic integration,” IEEE Micro, vol. 27, no. 4, pp. 6–20, 2007.
[CrossRef]

P. Gupta and N. McKeown, “Designing and implementing a fast crossbar scheduler,” IEEE Micro, vol. 19, no. 1, pp. 20–28, 1999.
[CrossRef]

IEEE Photon. Technol. Lett. (2)

B. G. Lee, B. A. Small, Q. F. Xu, M. Lipson, and K. Bergman, “Characterization of a 4 × 4 Gb/s parallel electronic bus to WDM optical link silicon photonic translator,” IEEE Photon. Technol. Lett., vol. 19, no. 5, pp. 456–458, 2007.
[CrossRef]

B. G. Lee, A. Biberman, D. Po, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photon. Technol. Lett., vol. 20, no. 10, pp. 767–769, 2008.
[CrossRef]

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, no. 9, pp. 1246–1260, 2008.
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IEEE/ACM Trans. Netw. (2)

N. McKeown, “The iSLIP scheduling algorithm for input-queued switches,” IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188–201, 1999.
[CrossRef]

I. Iliadis and C. Minkenberg, “Performance of a speculative transmission scheme for scheduling-latency reduction,” IEEE/ACM Trans. Netw., vol. 16, no. 1, pp. 182–195, 2008.
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J. Lightwave Technol. (1)

J. Opt. Commun. Netw. (1)

J. Opt. Netw. (1)

Nat. Photonics (1)

G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, “Silicon optical modulators,” Nat. Photonics, vol. 4, no. 8, pp. 518–526, 2010.
[CrossRef]

Opt. Express (1)

Opt. Lett. (1)

Proc. IEEE (2)

A. W. Poon, X. S. Luo, F. Xu, and H. Chen, “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE, vol. 97, no. 7, pp. 1216–1238, 2009.
[CrossRef]

D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, pp. 1166–1185, 2009.
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Other (15)

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, “Dark silicon and the end of multicore scaling,” in Proc. of the 38th Annu. Int. Symp. on Computer Architecture, 2011.

U. Vlasov, “Silicon photonics for next generation computing systems,” in European Conf. on Optical Communications (ECOC), 2008.

I. H. White and R. V. Penty, “Optical interconnects for backplane and chip-to-chip photonics,” in 2nd ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS ’08), 2008.

C. Minkenberg, I. Iliadis, and F. Abel, “Low-latency pipelined crossbar arbitration,” in IEEE Global Telecommunications Conf. (GLOBECOM), 2004, vol. 2, pp. 1174–1179.

R. Luijten, C. Minkenberg, R. Hemenway, M. Sauer, and R. Grzybowski, “Viable opto-electronic HPC interconnect fabrics,” in Proc. of the ACM/IEEE Supercomputing Conf., 2005.

K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. K. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. Walker, “On the feasibility of optical circuit switching for high performance computing systems,” in Proc. of the ACM/IEEE Supercomputing Conf. 2005.

C. Minkenberg, “Performance of i-SLIP scheduling with large round-trip latency,” in Workshop on High Performance Switching and Routing (HPSR), 2003.

A. Biberman, G. Hendry, J. Chan, H. Wang, K. Bergman, K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “CMOS-compatible scalable photonic switch architecture using 3D-integrated deposited silicon materials for high-performance data center networks,” in Proc. Optical Fiber Communications Conf., Mar. 2011.

W. N. Ye, R. Sun, J. Michel, L. Eldada, D. Pant, and L. C. Kimerling, “Thermo-optical compensation in high-index-contrast waveguides,” in 5th IEEE Int. Conf. on Group IV Photonics, 2008.

J. E. Cunningham, I. Shubin, X. Zheng, G. Li, H. Thacker, Y. Luo, J. Yao, K. Raj, B. Guenin, T. Pinguet, and A. V. Krishnamoorthy, “Compact, thermally-tuned resonant ring muxes in CMOS with integrated backside pyramidal etch pit,” in Proc. Optical Fiber Communication Conf. (OFC), 2011.

M. R. Reshotko, B. A. Block, B. Jin, and P. Chang, “Waveguide coupled Ge-on-oxide photodetectors for integrated optical links,” in 5th IEEE Int. Conf. on Group IV Photonics, 2008, pp. 182–184.

X. Zheng, F. Liu, J. Lexau, D. Patil, G. Li, Y. Luo, H. Thacker, I. Shubin, J. Yao, K. Raj, R. Ho, J. E. Cunningham, and A. V. Krishnamoorthy, “Ultra-low power arrayed CMOS silicon photonic transceivers for an 80 Gb/s WDM optical link,” in Proc. Optical Fiber Communications (OFC) Conf., Mar. 2011.

Y. Kuwana, S. Takenobu, K. Takayama, S. Yokotsuka, and S. Kodama, “Low loss and highly reliable polymer optical waveguides with perfluorinated dopant-free core,” in Optical Fiber Communication Conf. (OFC), Mar. 2006.

T. W. Y. Chen and R. Katz, “Energy efficient Ethernet encodings,” in 33rd IEEE Conf. on Local Computer Networks (LCN), Oct. 2008, pp. 122–129.

Y. Audzevich, P. M. Watts, S. Kilmurray, and A. W. Moore, “Efficient photonic coding: A considered revision,” in GreenNets 2011 (SIGCOM workshop), Aug. 2011.

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Figures (12)

Fig. 1
Fig. 1

(Color online) Rack-scale network of 3D integrated chip multiprocessors with distributed shared memory communications. For clarity the control path between network adapter and allocator is not shown.

Fig. 2
Fig. 2

(Color online) N-port iSLIP scheduled network model: (a) network schematic, (b) allocator detail.

Fig. 3
Fig. 3

(Color online) Timing diagrams for (a) scheduled transmission, (b) speculative transmission using the SPINet scheme and (c) pipelined speculative transmission. In each case, the dotted lines show the slot period boundaries defining the switching period. Request transmissions are timed to arrive at the switch at the start of the arbitration period.

Fig. 4
Fig. 4

(Color online) Detailed timing diagrams for successful packet transmissions using (a) scheduled and (b) speculative networks. The time of flight between the source port and the switch is 10 ns. In the speculative case, input port arbitration and packet dequeue take one clock cycle, which is 2.26 ns.

Fig. 5
Fig. 5

(Color online) Schematic diagrams of speculative network control circuits: (a) allocator, (b) network adapter transmitter side and (c) network adapter receiver side.

Fig. 6
Fig. 6

Comparison of the latency characteristics of scheduled and speculative networks with random traffic.

Fig. 7
Fig. 7

The number of transmissions per received packet for scheduled and speculative networks.

Fig. 8
Fig. 8

Minimum clock periods for the iSLIP and speculative allocator circuits using a commercial, low leakage 45 nm CMOS standard cell library.

Fig. 9
Fig. 9

Power consumption of 32-port allocator circuits under random traffic of varying load.

Fig. 10
Fig. 10

Power consumption of a single network adapter (for a 32-port network) under random traffic of varying load.

Fig. 11
Fig. 11

(Color online) Contributions to total power consumption of a 32-port network. PPS is the photonic power supply, which includes the power gating SOA. The control plane power includes the allocator and adapters.

Fig. 12
Fig. 12

(Color online) Contributions to the network power dissipated on the chip multiprocessor (CMP) for 32-port scheduled and speculative networks.

Tables (1)

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Table I Assumed Parameters for Power Modeling