Abstract

Future computer systems will require new levels of computing power and hence new levels of core and chip densities. Because of constraints on power and area, optical interconnection networks will play a critical role in these new systems. In this paper, we describe the macrochip, a multi-chip node with an embedded silicon photonic interconnection network that consists of thousands of optical links. For such a large-scale wavelength division multiplexing optical network, we show how to use an energy-efficient error control scheme employing variable-length cyclic redundancy check codes to achieve a desirable residual bit error rate (BER) of 1023 for reliable system operation with the individual link BER at 1012 or higher. We use a discrete-event network simulation of the macrochip using uniform random traffic to show that our scheme incurs minimal impact on performance compared to a perfect system with no error control. Using link level energy efficiency and network throughput analysis, we estimate and report network level energy efficiency using the metric of energy per useful bit.

© 2011 OSA

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  1. K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.
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  3. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).
  4. P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.
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  7. K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.
  8. J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.
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  24. R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.
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2009 (2)

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

2008 (1)

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

2004 (1)

R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits 39, (9), 1529‒1535 (2004).

2001 (1)

A. Burr, "Turbo-codes: the ultimate error control codes?," Electron. Commun. Eng. J. 13, (4), 155‒165 (2001).
[CrossRef]

1993 (1)

G. Castagnoli, S. Brauer, and M. Herrmann, "Optimization of cyclic redundancy-check codes with 24 and 32 parity bits," IEEE Trans. Commun. 41, (6), 883‒892 (1993).
[CrossRef]

1990 (1)

G. Castagnoli, J. Ganz, and P. Graber, "Optimum cyclic redundancy-check codes with 16-bit redundancy," IEEE Trans. Commun. 38, (1), 111‒114 (1990).
[CrossRef]

1960 (1)

I. S. Reed and G. Solomon, "Polynomial codes over certain finite fields," J. Soc. Indust. Appl. Math. 8, (2), 300‒304 (1960).
[CrossRef]

Alon, E.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Amann, J.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Amberg, P.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Anderson, W.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Antono, D.

K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

Asanovic, K.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Asghari, M.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

Bao, L.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Bell, S.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Benini, L.

D. Bertozzi, L. Benini, and G. D Micheli, "Low power error resilient encoding for on-chip data bus," Proc. 2002 Design, Automation and Test in Europe Conf. and Exhibition (DATE ’02), 4–8 Mar. 2002, pp. 102‒109.

Berger, E.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Bergman, K.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Bertozzi, D.

D. Bertozzi, L. Benini, and G. D Micheli, "Low power error resilient encoding for on-chip data bus," Proc. 2002 Design, Automation and Test in Europe Conf. and Exhibition (DATE ’02), 4–8 Mar. 2002, pp. 102‒109.

Bodik, R.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Bonifield, T.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Borkar, N.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Borkar, S.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Brauer, S.

G. Castagnoli, S. Brauer, and M. Herrmann, "Optimization of cyclic redundancy-check codes with 24 and 32 parity bits," IEEE Trans. Commun. 41, (6), 883‒892 (1993).
[CrossRef]

Brown, J.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Burr, A.

A. Burr, "Turbo-codes: the ultimate error control codes?," Electron. Commun. Eng. J. 13, (4), 155‒165 (2001).
[CrossRef]

Campbell, D.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Carlson, W.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Castagnoli, G.

G. Castagnoli, S. Brauer, and M. Herrmann, "Optimization of cyclic redundancy-check codes with 24 and 32 parity bits," IEEE Trans. Commun. 41, (6), 883‒892 (1993).
[CrossRef]

G. Castagnoli, J. Ganz, and P. Graber, "Optimum cyclic redundancy-check codes with 16-bit redundancy," IEEE Trans. Commun. 38, (1), 111‒114 (1990).
[CrossRef]

Catanzaro, B. C.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Chakravarty, T.

P. Koopman and T. Chakravarty, "Cyclic redundancy code (CRC) polynomial selection for embedded networks," Proc. 2004 Int. Conf. Dependable Systems and Networks, 2004, pp. 145‒154.

Conlin, R.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Cunningham, J.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.

Cunningham, J. E.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Dahlem, M.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Dally, W.

W. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004, p. 411.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Denneau, M.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Dighe, S.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Drost, R.

R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits 39, (9), 1529‒1535 (2004).

J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.

Edwards, B.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Erraguntla, V.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Fairbanks, N.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Feng, D.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

Finan, D.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Franzon, P.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Ganz, J.

G. Castagnoli, J. Ganz, and P. Graber, "Optimum cyclic redundancy-check codes with 16-bit redundancy," IEEE Trans. Commun. 38, (1), 111‒114 (1990).
[CrossRef]

Gao, S.

S. Gao, V. K. Bhargava, H. V. Poor, V. Tarokh, and S. Yoon, ed., Communications, Information and Network Security, Kluwer Academic, 2003, ch. 5.

Gebis, J. J.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Graber, P.

G. Castagnoli, J. Ganz, and P. Graber, "Optimum cyclic redundancy-check codes with 16-bit redundancy," IEEE Trans. Commun. 38, (1), 111‒114 (1990).
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P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Herrmann, M.

G. Castagnoli, S. Brauer, and M. Herrmann, "Optimization of cyclic redundancy-check codes with 24 and 32 parity bits," IEEE Trans. Commun. 41, (6), 883‒892 (1993).
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Hill, K.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Hiller, J.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Ho, R.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits 39, (9), 1529‒1535 (2004).

J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

Holzwarth, C.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Hopkins, R.

R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits 39, (9), 1529‒1535 (2004).

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Hoskote, Y.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Howard, J.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Hoyt, J.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Husbands, P.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Ippen, E.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Ishida, K.

K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

Jacob, T.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Jain, S.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Joyce, K.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Kanda, K.

K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

Karp, S.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Kartner, F.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Kawaguchi, H.

K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

Keckler, S.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Keutzer, K.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Khan, D.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Khilo, A.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Klein, D.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Kogge, P.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Koka, P.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

Koopman, P.

P. Koopman and T. Chakravarty, "Cyclic redundancy code (CRC) polynomial selection for embedded networks," Proc. 2004 Int. Conf. Dependable Systems and Networks, 2004, pp. 145‒154.

Krishnamoorthy, A. V.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Kung, C.-C.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

Kuroda, T.

K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

Leung, V.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Lexau, J.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Li, G.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

Li, H.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Liang, H.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

Liu, F.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Lucas, R.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

MacKay, J.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Mattina, M.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

McCracken, M. O.

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

Miao, C.-C.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Micheli, G. D

D. Bertozzi, L. Benini, and G. D Micheli, "Low power error resilient encoding for on-chip data bus," Proc. 2002 Design, Automation and Test in Europe Conf. and Exhibition (DATE ’02), 4–8 Mar. 2002, pp. 102‒109.

Mitchell, J.

J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.

Montenegro, F.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Moss, B.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

O’Krafka, B.

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

Orcutt, J.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Patil, D.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Patterson, D. A.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Pinckney, N.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Plishker, W. L.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Popovic, M.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Ram, R.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Ramey, C.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Reed, I. S.

I. S. Reed and G. Solomon, "Polynomial codes over certain finite fields," J. Soc. Indust. Appl. Math. 8, (2), 300‒304 (1960).
[CrossRef]

Reif, M.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Richards, M.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Roberts, C.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Roman, S.

S. Roman, J. H. Ewing, F. W. Gehring, and P. R. Halmos, ed., Coding and Information Theory, Springer-Verlag, 1992, pp. 253‒278ch. 6.

Ruhl, G.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Sakurai, T.

K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

Scarpelli, A.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Schwetman, H.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

Scott, S.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Shafter, M. S.

L. Song, M. Yu, and M. S. Shafter, "A 10 Gb/s and 40 Gb/s forward-error-correction device for optical communications," ISSCC, 2002, pp. 415‒416.

Shalf, J.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Shubin, I.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

Simons, J.

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

Singh, A.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Snavely, A.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Solomon, G.

I. S. Reed and G. Solomon, "Polynomial codes over certain finite fields," J. Soc. Indust. Appl. Math. 8, (2), 300‒304 (1960).
[CrossRef]

Song, L.

L. Song, M. Yu, and M. S. Shafter, "A 10 Gb/s and 40 Gb/s forward-error-correction device for optical communications," ISSCC, 2002, pp. 415‒416.

Sterling, T.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Stickney, J.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Stojanovic, V.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

Sutherland, I.

R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits 39, (9), 1529‒1535 (2004).

Towles, B.

W. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004, p. 411.

Tschanz, J.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Vangal, S.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Wentzlaff, D.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

Williams, R.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Williams, S. W.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Wilson, H.

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

Yelick, K.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

Yelick, K. A.

K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

Yu, M.

L. Song, M. Yu, and M. S. Shafter, "A 10 Gb/s and 40 Gb/s forward-error-correction device for optical communications," ISSCC, 2002, pp. 415‒416.

Zheng, X.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

Zook, J.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

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[CrossRef]

IEEE J. Quantum Electron. (1)

A. V. Krishnamoorthy, J. E. Cunningham, X. Zheng, I. Shubin, J. Simons, D. Feng, H. Liang, C.-C. Kung, and M. Asghari, "Optical proximity communication with passively aligned silicon photonic chips," IEEE J. Quantum Electron. 45, (4), 409‒414 (2009).
[CrossRef]

IEEE J. Solid-State Circuits (2)

R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits 39, (9), 1529‒1535 (2004).

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, "An 80- tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits 43, (1), 29‒41 (2008).

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[CrossRef]

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A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. Li, I. Shubin, and J. Cunningham, "Computer systems based on silicon photonic interconnects," Proc. IEEE 97, (7), 1337‒1361 (2009).
[CrossRef]

Other (19)

P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon–photonic network architectures for scalable, power-efficient multi-chip systems," Proc. 37th Annu. Int. Symp. Computer Architecture, 2010, pp. 117‒128.

W. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004, p. 411.

J. Orcutt, A. Khilo, M. Popovic, C. Holzwarth, B. Moss, H. Li, M. Dahlem, T. Bonifield, F. Kartner, E. Ippen, J. Hoyt, R. Ram, and V. Stojanovic, "Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process," Conf. on Lasers and Electro-Optics (CLEO), 2008, CTuBB3.

P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. Williams, and K. Yelick, "Exascale computing study: technology challenges in achieving exascale systems," DARPA IPTO Report, 2008.

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K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: a view from Berkeley," Tech. Rep. UCB/EECS-2006-183, EECS, UC Berkeley, 2006.

S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, "Tile64-processor: a 64-core SoC with mesh interconnect," ISSCC, 2008, pp. 88‒598.

L. Song, M. Yu, and M. S. Shafter, "A 10 Gb/s and 40 Gb/s forward-error-correction device for optical communications," ISSCC, 2002, pp. 415‒416.

D. Bertozzi, L. Benini, and G. D Micheli, "Low power error resilient encoding for on-chip data bus," Proc. 2002 Design, Automation and Test in Europe Conf. and Exhibition (DATE ’02), 4–8 Mar. 2002, pp. 102‒109.

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K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," ISSCC, Vol. 1, 2003, pp. 186‒487.

J. Mitchell, J. Cunningham, A. V. Krishnamoorthy, R. Drost, and R. Ho, "Integrating novel packaging technologies for large scale computer systems," ASME/Pacific Rim Technical Conf. and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK 2009), June 2009, pp. 57‒66.

A. V. Krishnamoorthy, R. Ho, B. O’Krafka, J. E. Cunningham, J. Lexau, and X. Zheng, "Potentials of group IV photonics interconnects for ‘red-shift’ computing applications," 4th IEEE Int. Conf. on Group IV Photonics, 2007, pp. 180‒182PLE2.1.

P. Koopman and T. Chakravarty, "Cyclic redundancy code (CRC) polynomial selection for embedded networks," Proc. 2004 Int. Conf. Dependable Systems and Networks, 2004, pp. 145‒154.

R. Ho, J. Lexau, F. Liu, D. Patil, R. Hopkins, E. Alon, N. Pinckney, P. Amberg, X. Zheng, J. E. Cunningham, and A. V. Krishnamoorthy, "Circuits for silicon photonics on a ‘macrochip’," IEEE Asian Solid-State Circuits Conf., Nov. 2009.

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Figures (13)

Fig. 1
Fig. 1

(Color online) Diagram of an 8 × 8 macrochip.

Fig. 2
Fig. 2

(Color online) 2 × 2 static WDM point-to-point network.

Fig. 3
Fig. 3

Simplified block diagram of a macrochip WDM photonic link with an off-chip laser source. The receiver is represented by a photodetector and a transimpedance amplifier. Limiting amplifier stages and the clock and data recovery circuit that typically follows the receiver are not shown.

Fig. 4
Fig. 4

(Color online) Undetected error probability for Hamming codes.

Fig. 5
Fig. 5

(Color online) Undetected error probability of CRC codes for 8-byte packets.

Fig. 6
Fig. 6

(Color online) Undetected error probability of CRC codes for 64-byte packets.

Fig. 7
Fig. 7

(Color online) Undetected error probability of CRC codes for 4096-byte packets.

Fig. 8
Fig. 8

Data packet format used in the simulation.

Fig. 9
Fig. 9

(Color online) Simulated error control protocol.

Fig. 10
Fig. 10

(Color online) 8-byte performance and buffer requirement plots: (a) latency versus load plot; (b) buffers per port versus load plot.

Fig. 11
Fig. 11

(Color online) 64-byte performance and buffer requirement plots: (a) latency versus load plot; (b) buffers per port versus load plot.

Fig. 12
Fig. 12

(Color online) 4096-byte performance and buffer requirement plots: (a) latency versus load plot; (b) buffers per port versus load plot.

Fig. 13
Fig. 13

(Color online) Energy per useful bit versus payload size.

Tables (2)

Tables Icon

Table I Macrochip System Parameters

Tables Icon

Table II Summary of Values Used for Error Control

Equations (4)

Equations on this page are rendered with MathJax. Learn more.

Energy/Useful Bit = Power Payload/Delivery Time .
Power Link = P receiver + P transmitter + P WDM + P Laser .
P Laser = 2 P sens IL Link ( E r + 1 ) ( E r 1 ) Q Q 0 1 η Laser ,
Energy/Useful Bit = Total Power Network Throughput .