Abstract

Although a great deal of research has been carried out over the last decade in which many different approaches for devising optoelectronic interconnects have been proposed, more detailed analysis of the performance parameters such as power, latency, and area of different optical technologies is yet to be done. Optoelectronics offer potential for new approaches to the production of VLSI interconnects, but previous works have made overly simplified assumptions for optoelectronic interconnections. In this paper, we present a preliminary analysis of the system parameters of different optoelectronic interconnect technologies. Based on our analysis, we conclude that the three-dimensional free-space optoelectronic interconnect network has the best speed area product performance compared with fiber-optical interconnects and optical microelectromechanical systems (MEMS) interconnects. Second, although the optoelectronic interconnect offers higher data rates and less power per bit compared with electronic interconnects, the bipolar encoding scheme on the source plane and the detector plane means that a larger area and volume will be needed.

© 2010 Optical Society of America

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D. A. B. Miller, “Device requirements for optical interconnects to silicon chips,” Proc. IEEE, vol. 97, no. (7), pp. 1166–1185, July 2009.
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L. Tsybeskov, D. J. Lockwood, M. Ichikawa, “Silicon photonics: CMOS going optical,” Proc. IEEE, vol. 97, no. 7, pp. 1161–1165, July 2009.
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L. Chen, K. Preston, S. Manipatruni, M. Lipson, “Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors,” Opt. Express, vol. 17, no. 17, pp. 15248–15256, Aug. 2009.
[CrossRef] [PubMed]

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

D. Lu, “Recent advances on chip-to-chip optical interconnect,” Proc. SPIE, vol. 7516, paper 75160O, 2009.
[CrossRef]

A. K. Kodi, A. Louri, “Multidimensional and reconfigurable optical interconnects for high-performance computing (HPC) systems,” J. Lightwave Technol., vol. 27, no. 21, pp. 4634–4641, Nov. 2009.
[CrossRef]

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE, vol. 97, no. 7, pp. 1337–1361, July 2009.
[CrossRef]

2007 (1)

X. Zheng, J. K. Lexau, J. Bergey, J. E. Cunningham, R. Ho, R. D. Ashok, A. V. Krishnamoorthy, “Optical transceiver chips based on co-integration of capacitively coupled proximity interconnects and VCSELS,” IEEE Photon. Technol. Lett., vol. 19, no. 7, pp. 453–455, Apr. 2007.
[CrossRef]

2004 (3)

2002 (1)

2000 (3)

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE, vol. 88, no. 6, pp. 728–749, June 2000.
[CrossRef]

Y. Li, J. Popelek, “Volume-consumption comparisons of free-space and guided-wave optical interconnections,” Appl. Opt., vol. 39, no. 11, pp. 1815–1825, Apr. 2000.
[CrossRef]

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

1999 (2)

H. M. Ozaktas, F. F. Erden, “Comparison of fully three-dimensional optical, normally conducting, and superconducting interconnections,” Appl. Opt., vol. 38, no. 35, pp. 7264–7275, Dec. 1999.
[CrossRef]

J. Popelek, Y. Li, “Free-space fiber hybrid distributed optical cross-connect interconnect module,” Opt. Lett., vol. 24, pp. 42–44, 1999.
[CrossRef]

1997 (3)

1996 (2)

1995 (1)

J. Fan, D. Zaleta, C.-K. Cheng, S. H. Lee, “Physical models and algorithms for optoelectronic MCM layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 1, pp. 124–135, Mar. 1995.
[CrossRef]

1994 (3)

T. J. Drabik, “Optoelectronic integrated systems based on free-space interconnects with arbitrary degree of space variance,” Proc. IEEE, vol. 82, no. 11, pp. 1595–1622, 1994.
[CrossRef]

H. S. Hinton, T. J. Cloonan, F. B. McCormick, A. L. Lentine, F. A. P. Tooley, “Free-space digital optical systems,” Proc. IEEE, vol. 82, no. 11, pp. 1632–1649, Nov. 1994.
[CrossRef]

T.-H. Lin, “Implementation and characterization of a flexture-beam micromechanical spatial light modulator,” Opt. Eng. (Bellingham), vol. 33, no. 1, pp. 3643–3648, Nov. 1994.
[CrossRef]

1993 (1)

1991 (1)

H. M. Ozaktas, Y. Amitai, J. W. Goodman, “Comparison of system size for some optical interconnection architectures and the folded multi-facet architecture,” Opt. Commun., vol. 82, no. 4, pp. 225–228, Apr. 1991.
[CrossRef]

1988 (1)

1987 (2)

R. K. Kostuk, J. W. Goodman, L. Hesselink, “Design considerations for holographic optical interconnects,” Appl. Opt., vol. 26, pp. 3947–3953, 1987.
[CrossRef] [PubMed]

Y. Amita, A. A. Friesem, “Recursive design techniques for Fourier transform holographic lenses,” Opt. Eng. (Bellingham), vol. 26, no. 11, pp. 1133–1139, Nov. 1987.

1985 (2)

J. W. Goodman, F. J. Leonberger, S. Y. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE, vol. 72, pp. 850–875, 1985.
[CrossRef]

R. K. Kostuk, J. W. Goodman, L. Hesselink, “Optical imaging applied to microelectronic chip-to-chip interconnections,” Appl. Opt., vol. 24, no. 17, pp. 2851–2858, Sept. 1985.
[CrossRef] [PubMed]

1984 (1)

1979 (1)

J. R. Leger, S. H. Lee, “Coherent optical implementation of generalized two-dimensional transform,” Opt. Eng. (Bellingham), vol. 18, no. 5, 1979.
[CrossRef]

1975 (1)

C. Edwards, “The application of the Rademacher-Walsh transform to Boolean Classification,” IEEE Trans. Comput., vol. C-24, no. 1, Jan. 1975.
[CrossRef]

1973 (1)

S. L. Hurst, “The application of Chow parameters and Rademacher-Walsh matrices in the synthesis of binary functions,” Comput. J., vol. 16, pp. 165–173, 1973.
[CrossRef]

1970 (1)

R. Lechner, “A transform approach to logic design,” IEEE Trans. Comput., vol. C-19, no. 7, July 1970.
[CrossRef]

Agarwar, D.

D. Agarwar, “Optical interconnects to silicon chips using short pulses,” Ph.D. dissertation, Standford Univ., 2002, p. 36, p. 54.

Akedo, J.

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Amita, Y.

Y. Amita, A. A. Friesem, “Recursive design techniques for Fourier transform holographic lenses,” Opt. Eng. (Bellingham), vol. 26, no. 11, pp. 1133–1139, Nov. 1987.

Amitai, Y.

H. M. Ozaktas, Y. Amitai, J. W. Goodman, “Comparison of system size for some optical interconnection architectures and the folded multi-facet architecture,” Opt. Commun., vol. 82, no. 4, pp. 225–228, Apr. 1991.
[CrossRef]

Ashok, R. D.

X. Zheng, J. K. Lexau, J. Bergey, J. E. Cunningham, R. Ho, R. D. Ashok, A. V. Krishnamoorthy, “Optical transceiver chips based on co-integration of capacitively coupled proximity interconnects and VCSELS,” IEEE Photon. Technol. Lett., vol. 19, no. 7, pp. 453–455, Apr. 2007.
[CrossRef]

Athale, R. A.

J. W. Goodman, F. J. Leonberger, S. Y. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE, vol. 72, pp. 850–875, 1985.
[CrossRef]

Baker, J.

J. Baker, CMOS Circuit Design, Layout, and Simulation, revised 2nd ed.Wiley Interscience, 2008.

Bare, H. F.

F. Haas, D. A. Honey, H. F. Bare, “Optical interconnects for 3D computer architectures,” U.S. Airforce Rome Laboratory in-house report, RL-TR-94-227, Dec. 1994.

Bergey, J.

X. Zheng, J. K. Lexau, J. Bergey, J. E. Cunningham, R. Ho, R. D. Ashok, A. V. Krishnamoorthy, “Optical transceiver chips based on co-integration of capacitively coupled proximity interconnects and VCSELS,” IEEE Photon. Technol. Lett., vol. 19, no. 7, pp. 453–455, Apr. 2007.
[CrossRef]

Born, M.

M. Born, E. Wolf, Principles of Optics. Cambridge U. Press, 1980.

Bristow, J.

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

Carharta, G.

J. J. Liu, B. Gollsneider, W. Changa, G. Carharta, M. L. Vorontsova, G. J. Simonisa, B. L. Shoop, “Two-dimensional opto-electronic interconnect-processor and its operational bit-error-rate,” Proc. SPIE, vol. 5595, pp. 153–161, 2004.
[CrossRef]

Celik, M.

M. Celik, L. Pileggi, A. Odabasioglu, IC Interconnct Analysis. Kluwer Academic, 2002.

Chang, N.

C.-K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis. Wiley, 2000.

Changa, W.

J. J. Liu, B. Gollsneider, W. Changa, G. Carharta, M. L. Vorontsova, G. J. Simonisa, B. L. Shoop, “Two-dimensional opto-electronic interconnect-processor and its operational bit-error-rate,” Proc. SPIE, vol. 5595, pp. 153–161, 2004.
[CrossRef]

Chen, L.

Chen, R. T.

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

Cheng, C.-K.

J. Fan, D. Zaleta, C.-K. Cheng, S. H. Lee, “Physical models and algorithms for optoelectronic MCM layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 1, pp. 124–135, Mar. 1995.
[CrossRef]

C.-K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis. Wiley, 2000.

Cho, H.

Choi, C.

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

Cloonan, T. J.

H. S. Hinton, T. J. Cloonan, F. B. McCormick, A. L. Lentine, F. A. P. Tooley, “Free-space digital optical systems,” Proc. IEEE, vol. 82, no. 11, pp. 1632–1649, Nov. 1994.
[CrossRef]

Cunningham, J. E.

A. V. Krishnamoorthy, R. Ho, X. Zheng, H. Schwetman, J. Lexau, P. Koka, G. L. Li, I. Shubin, J. E. Cunningham, “Computer systems based on silicon photonic interconnects,” Proc. IEEE, vol. 97, no. 7, pp. 1337–1361, July 2009.
[CrossRef]

X. Zheng, J. K. Lexau, J. Bergey, J. E. Cunningham, R. Ho, R. D. Ashok, A. V. Krishnamoorthy, “Optical transceiver chips based on co-integration of capacitively coupled proximity interconnects and VCSELS,” IEEE Photon. Technol. Lett., vol. 19, no. 7, pp. 453–455, Apr. 2007.
[CrossRef]

Drabik, T. J.

T. J. Drabik, “Optoelectronic integrated systems based on free-space interconnects with arbitrary degree of space variance,” Proc. IEEE, vol. 82, no. 11, pp. 1595–1622, 1994.
[CrossRef]

Edwards, C.

C. Edwards, “The application of the Rademacher-Walsh transform to Boolean Classification,” IEEE Trans. Comput., vol. C-24, no. 1, Jan. 1975.
[CrossRef]

Edwards, C. R.

C. R. Edwards, “The application of the Rademacher-Walsh transform to digital circuit synthesis,” in Theory and Applications of Walsh and Other Sinusoidal Functions, 1973.

Erden, F. F.

Esener, S.

G. Li, S. Esener, “Parallel free-space optical interconnection,” in Optical Switching/Networking and Computing for Multimedia Systems, M. Guizani and A. Battou, Eds. CRC Press, 2002, ch. 10, pp. 301–370.

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K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Tang, S.

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

Tooley, F. A. P.

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K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Tsuchizawa, T.

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Tsybeskov, L.

L. Tsybeskov, D. J. Lockwood, M. Ichikawa, “Silicon photonics: CMOS going optical,” Proc. IEEE, vol. 97, no. 7, pp. 1161–1165, July 2009.
[CrossRef]

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K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Ushida, J.

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Vorontsova, M. L.

J. J. Liu, B. Gollsneider, W. Changa, G. Carharta, M. L. Vorontsova, G. J. Simonisa, B. L. Shoop, “Two-dimensional opto-electronic interconnect-processor and its operational bit-error-rate,” Proc. SPIE, vol. 5595, pp. 153–161, 2004.
[CrossRef]

Watanabe, T.

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Wickman, R.

R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

Wolf, E.

M. Born, E. Wolf, Principles of Optics. Cambridge U. Press, 1980.

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R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Hihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. Hibbs-Brenner, J. Bristow, Y. S. Liu, “Fully embedded board-level guided-wave optoelectronic interconnects,” Proc. IEEE, vol. 88, no. 6, pp. 780–793, June 2000.
[CrossRef]

Yamada, K.

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

Yuceturk, E.

Yukawa, H.

K. Ohashi, K. Nishi, T. Shimizu, M. Nakada, J. Fujikata, J. Ushida, S. Torii, K. Nose, M. Mizuno, H. Yukawa, M. Kinoshita, N. Suzuki, A. Ganyo, T. Ishi, D. Okamato, K. Furue, T. Ueno, T. Tsuchizawa, T. Watanabe, K. Yamada, S.-I. Itabashi, J. Akedo, “On-chip optical interconnect,” Proc. IEEE, vol. 97, no. 7, pp. 1186–1198, July 2009.
[CrossRef]

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Figures (22)

Fig. 1
Fig. 1

Multiprocessor block diagram.

Fig. 2
Fig. 2

Bus arbiter circuit.

Fig. 3
Fig. 3

Optoelectronic pipeline architecture and logic timing constraints.

Fig. 4
Fig. 4

Two-to-one multiplexer diagram.

Fig. 5
Fig. 5

Binary truth table for a two-to-one multiplexer diagram.

Fig. 6
Fig. 6

Detector arrays and comparator.

Fig. 7
Fig. 7

Circuit to implement a two-variable Boolean basis vector [36].

Fig. 8
Fig. 8

Circuit to implement a three-variable Boolean basis vector [36].

Fig. 9
Fig. 9

Circuit to implement a five-variable Boolean basis vector.

Fig. 10
Fig. 10

Traditional free-space optoelectronic interconnection.

Fig. 11
Fig. 11

Input plane—sources, polymer waveguide clock, and the latch.

Fig. 12
Fig. 12

Optical input array plane, normally constructed with VCSEL arrays with XOR gates and CMOS driver circuits [14].

Fig. 13
Fig. 13

Optical detector plane, normally constructed with photodector arrays and additional logic circuits [14].

Fig. 14
Fig. 14

Microscale 3-D free-space holographic interconnection network.

Fig. 15
Fig. 15

Structure of the CMOS two-stage op-amp with nulling resistance compensation.

Fig. 16
Fig. 16

Open-loop frequency response of the designed op-amp.

Fig. 17
Fig. 17

Closed-loop transient response of the designed op-amp.

Fig. 18
Fig. 18

Structure of the CMOS high-speed comparator with buffered output.

Fig. 19
Fig. 19

DC transfer characteristics of the designed comparator.

Fig. 20
Fig. 20

Overall receiver transient simulation.

Fig. 21
Fig. 21

Optoelectronic MEMS interconnect diagram.

Fig. 22
Fig. 22

DMD single-cell diagram.

Tables (4)

Tables Icon

Table 1 Two Input Variables Showing the Truth-Table Interconnection Pattern for the DMD-CGH Optical MEMS Interconnection System

Tables Icon

Table 2 Comparison of Area and Latency of Different Optoelectronic Interconnects

Tables Icon

Table 3 Comparison of Power Consumptions of Different Optoelectronic Interconnects

Tables Icon

Table 4 System Symbols Used in the Calculations

Equations (39)

Equations on this page are rendered with MathJax. Learn more.

T hold T comb T T setup .
T comb N ( t d + t s ) .
T hold N ( t d + t s ) T T setup ,
y k = f k ( x 1 , x 2 , x 3 , , x m ) , k = 1 , 2 , 3 , , n .
1 0 1 0 1 0 1 0 × 1 + 1 1 + 1 1 + 1 1 + 1
[ Y ] = p = 0 2 m 1 [ X p ( x i ) ] [ S p ( x i ) ] ,
[ S p ( x i ) ] = 1 2 m [ T m ] [ Y ] ,
[ Z ] = p = 0 2 m 1 [ r p ( z i ) ] [ R p ( z i ) ] ,
[ R p ( z i ) ] = 1 2 m [ T m ] [ Z ] ,
z i = 1 2 x i ,
R = T Z = 1 8 [ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ] [ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ] = 1 8 [ 0 6 6 6 6 6 6 6 0 2 2 2 2 2 2 2 4 2 2 2 2 2 2 2 4 2 2 2 2 2 2 2 4 2 2 2 2 2 2 2 4 2 2 2 2 2 2 2 0 2 2 2 2 2 2 2 0 2 2 2 2 2 2 2 ] = [ 0 0.7500 0.7500 0.7500 0.7500 0.7500 0.7500 0.7500 0 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.5000 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.5000 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.5000 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.5000 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 0.2500 ] ,
r p ( z i ) = [ R 0 R 3 R 2 R 2 R 3 R 1 R 1 R 3 R 1 R 2 R 1 R 2 R 3 ] , X P ( x i ) = [ 1 x 3 x 2 x 2 x 3 x 1 x 1 x 3 x 1 x 2 x 1 x 2 x 3 ] .
V + = ( 1 + R f R N 1 ) ( R P R P 1 V D + + + R P R P 2 V D ) ,
R P = R P 1 R P 2 R P 1 + R P 2 .
V O = A d ( V + V ) + A CM ( V + + V 2 ) ,
CMRR = 20 log | A d | | A CM | ,
t delay 0.35 R N C O X N N 2 ,
d s = 2.44 λ f D .
A s = [ W s + ( 2 m + 1 1 ) d s ] [ W s + ( 2 N 1 ) d s ] + A XOR N .
d D = 2.44 λ f D ,
A D = [ W D + ( 2 n 1 ) d D ] [ W D + ( 2 N 1 ) d D ] + ( A cmps + A adders ) × n N .
A 3 D = A s + A D .
V 3 D = 1 2 ( A S + A D ) × 4 f .
P 3 D = 2 m + 2 N P S + n N × 4 P d + P XOR + P cmps + P adders ( 2 m + 2 P S + 4 n P d ) × N .
t 3 D = t s + t D + t XOR + t cmps + t adders .
GBW = g m 1 C C ,
PM = 90 ° arctan ( g m 1 g m 3 C L C C ) + arctan [ g m 1 g m 3 ( ( W L ) 3 ( W L ) 11 ( W L ) 9 ( W L ) 10 1 ) ] ,
f o = D 2 h 2 π L 2 E 12 ρ .
t DMD = 2 π L 2 D 2 h 12 ρ E ,
P = ( P S + 2 P DMD + 4 P D ) l .
W base = A s + 4 A D + 2 A DMD + 6 d ,
A MEM = W base l ,
t = t s + t D + 2 t DMD .
A OF = N C ( A S + A D ) + A electronic ,
t OF = t S + t D + t electronic .
A Fresnel = N C ( A S + A D ) + A electronic ,
t fresnel = t S + t D + t electronic .
P OF = N C ( P S + P D ) + P electronic ,
P Fresnel = N C ( P S + P D ) + P electronics .