It is widely recognized that in the new generation of photonic terabit packet routers optical integrated circuits will play a fundamental role for minimizing the cost of ownership, footprint, and power consumption of high-speed photonic interfaces. We review the present and future technologies for optical packet router architectures and the specific applications for photonic integrated circuits. Three technologies are today used for implementing optical integration: (a) monolithic InP integration allows all passive and active functions to be performed on the same chip with a minimum footprint but can raise issues of yield and scalability in bit rate; (b) hybrid , in which the only functionality left to InP is the emitter, provides moderate yield performances but good results in terms of footprint and scalability in bit rate; (c) hybrid InP/silica, in which all active functionalities are performed in InP and all the passive in silica, is very well performing in terms of yield but has a large footprint and limited scalability in bit rate, which could be a limitation in certain applications.
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