Abstract

An optoelectronic three-stage packet switch architecture is described that plays to the strengths of electronics as a memory technology and to photonics as a communications technology while accommodating the relatively slow reconfiguration of current transparent photonic switch technology. The configuration of the photonic center stage is found by solving an edge-coloring problem on a bipartite graph defined by the traffic. This is simple to implement, and the calculation need be repeated only if there are persistent variations in the statistical pattern of the arriving traffic. A major bottleneck is removed by dispensing with a per-time slot scheduler, at the price of only a modest spatial speedup, which is easy to provide with photonic technology. The architecture and method have been verified by simulation with simple traffic models that capture the nonstationary and bursty nature of real traffic

© 2005 Optical Society of America

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