Abstract

Market forecasts for intra and inter data center interconnects predict high growth rates in the upcoming years. This is associated with increasing requirements in terms of costs, power consumption, and bit rate per wavelength. Today, PAM4 systems are frequently used at up to 100 Gb/s per wavelength. The next logical step is to double the symbol rate to allow bit rates of 200 Gb/s at the same modulation format and at the same direct detection scheme. Such systems require three-digit gigasample analog-to-digital converters with bandwidths larger than 50 GHz, which are not available today as CMOS components. To extend the bandwidth of CMOS converters, we suggest the use of ADC frontends, which sample and demultiplex the analog input signals simultaneously. At the outputs of such ADC frontends, the signals can then be digitized by parallel converters with lower bandwidth and at a lower conversion rate. In this article, we present the circuit implementation of a 1-to-4 ADC frontend in IHP 130 nm SiGe HBT BiCMOS and demonstrate its integration into a 100 GBaud PAM4 transmission system with only 14 GHz of digitizer bandwidth. For optimum performance, the mitigation of intersymbol and interchannel interferences is mandatory in the transmission system. We describe and compare two different receiver DSP architectures for reduction of these interferences and evaluate their performances in electrical and optical back-to-back experiments. Furthermore, we report on transmission experiments over 500 m, 10 km, and 40 km SMF at 1550 nm wavelength. With linear equalization, we obtained a BER below the HD-FEC threshold of 3.8 × 10−3 and with 3rd order Volterra equalization, we even achieved a BER below the KP4 threshold of 2.3 × 10−4.

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