Abstract

We successfully developed a high-density broadband 16-channel × 25 Gb/s on-package silicon photonics optical transceiver. The flip chip bonded bridge structure realized high density of about 363 Gb/s/cm2. We demonstrated simultaneously on all 16 channels error-free operations with low crosstalk penalties of Tx-to-Tx 1.4 dB, Rx-to-Rx 1.4 dB, and Tx-to-Rx <0.1 dB.

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  1. S. Scott, “Optical interconnects in future HPC systems,” in Proc. Opt. Fiber Commun. Conf. Expo. Nat. Fiber Opt. Eng. Conf., 2011, Paper OWH5.
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  13. S. Tanakaet al., “Ultra-low-power (1.59 mW/Gbps), 56-Gbps PAM4 operation of Si photonic transmitter integrating segmented PIN Mach-Zehnder modulator and 28-nm CMOS driver,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper Th.1.C.1.
  14. T. Akiyama, S. Tanaka, and S. Sekiguchi, “A novel ultralow power consumption transmitter having a laser injection-locked by a silicon microring modulator,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper M.1.C.1.
  15. P. De Dobbelaere, “Silicon photonics transceivers for hyper‐scale datacenters: Deployment and roadmap,” 2016. [Online]. Available: http://www.phoxtrot.eu/wp-content/uploads/2017/01/ECOC-2016-Peter-De-Dobbelaere.pdf
  16. G. Denoyeret al., “Hybrid silicon photonic circuits and transceiver for 50 Gb/s NRZ transmission over single-mode fiber,” J. Lightw. Technol., vol. 33, no. 6, pp. 1247–1254, 2015.
  17. M. Rakowskiet al., “A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver,” in Proc. Int. Solid-State Circuits Conf., 2015, pp. 408–410.

2015 (2)

E. J. Fluhret al., “The 12-core POWER8 processor With 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking,” IEEE J. Solid-State Circuit, vol. 50, no. 1, pp. 10–23, 2015.

G. Denoyeret al., “Hybrid silicon photonic circuits and transceiver for 50 Gb/s NRZ transmission over single-mode fiber,” J. Lightw. Technol., vol. 33, no. 6, pp. 1247–1254, 2015.

2014 (1)

J. Verbruggheet al., “Multichannel 25 Gb/s low-Power Driver and transimpedance amplifier Integrated Circuits for 100 Gb/s Optical Links,” J. Lightw. Technol., vol. 32, no. 16, pp. 2877–2885, Aug. 2014.

2009 (1)

D. G. Kamet al., “Is 25 Gb/s on-board signaling viable?” IEEE Trans. Adv. Packag., vol. 32, no. 2, pp. 328–344, 2009.

Akiyama, T.

T. Akiyama, S. Tanaka, and S. Sekiguchi, “A novel ultralow power consumption transmitter having a laser injection-locked by a silicon microring modulator,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper M.1.C.1.

Aoki, T.

T. Aokiet al., “Low Crosstalk Simultaneous 12 ch × 25 Gb/s operation of high-density silicon photonics multichannel receiver,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2017, Paper Th1G.2.

T. Aokiet al., “Low crosstalk simultaneous 16-channel × 25 Gb/s operation of high density silicon photonics optical transceiver,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper Tu.1.C.3.

Chen, Y.

Y. Chenet al., “A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI,” in Proc. IEEE Int. Solid-State Circuits Conf., 2015, pp. 402–404.

De Dobbelaere, P.

P. De Dobbelaere, “Silicon photonics transceivers for hyper‐scale datacenters: Deployment and roadmap,” 2016. [Online]. Available: http://www.phoxtrot.eu/wp-content/uploads/2017/01/ECOC-2016-Peter-De-Dobbelaere.pdf

Denoyer, G.

G. Denoyeret al., “Hybrid silicon photonic circuits and transceiver for 50 Gb/s NRZ transmission over single-mode fiber,” J. Lightw. Technol., vol. 33, no. 6, pp. 1247–1254, 2015.

Fluhr, E. J.

E. J. Fluhret al., “The 12-core POWER8 processor With 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking,” IEEE J. Solid-State Circuit, vol. 50, no. 1, pp. 10–23, 2015.

Hatori, N.

N. Hatori, M. Kurihara, M. Nishizawa, Y. Tanaka, and K. Kurata, “A multi-channel light source on silicon substrate by flip-chip bonding,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

M. Nishizawa, N. Hatori, Y. Tanaka, M. Kurihara, and K. Kurata, “Packaging of 16ch (4ch × 4) integrated light sources with laser diode arrays on silicon platform,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

Hayakawa, A.

A. Hayakawaet al., “A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2015, Paper Th1G.2.

Ide, S.

T. Shiraishi, H. Oku, Y. Tsunoda, and S. Ide, “A 4 × 25.8-Gbps -13.7-dBm sensitivity optical receiver with <0.3 dB crosstalk penalty for 100-G short-reach application,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2016, Paper Th4D.

Kam, D. G.

D. G. Kamet al., “Is 25 Gb/s on-board signaling viable?” IEEE Trans. Adv. Packag., vol. 32, no. 2, pp. 328–344, 2009.

Kurata, K.

N. Hatori, M. Kurihara, M. Nishizawa, Y. Tanaka, and K. Kurata, “A multi-channel light source on silicon substrate by flip-chip bonding,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

M. Nishizawa, N. Hatori, Y. Tanaka, M. Kurihara, and K. Kurata, “Packaging of 16ch (4ch × 4) integrated light sources with laser diode arrays on silicon platform,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

Kurihara, M.

M. Nishizawa, N. Hatori, Y. Tanaka, M. Kurihara, and K. Kurata, “Packaging of 16ch (4ch × 4) integrated light sources with laser diode arrays on silicon platform,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

N. Hatori, M. Kurihara, M. Nishizawa, Y. Tanaka, and K. Kurata, “A multi-channel light source on silicon substrate by flip-chip bonding,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

Nishizawa, M.

N. Hatori, M. Kurihara, M. Nishizawa, Y. Tanaka, and K. Kurata, “A multi-channel light source on silicon substrate by flip-chip bonding,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

M. Nishizawa, N. Hatori, Y. Tanaka, M. Kurihara, and K. Kurata, “Packaging of 16ch (4ch × 4) integrated light sources with laser diode arrays on silicon platform,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

Oku, H.

T. Shiraishi, H. Oku, Y. Tsunoda, and S. Ide, “A 4 × 25.8-Gbps -13.7-dBm sensitivity optical receiver with <0.3 dB crosstalk penalty for 100-G short-reach application,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2016, Paper Th4D.

Rakowski, M.

M. Rakowskiet al., “A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver,” in Proc. Int. Solid-State Circuits Conf., 2015, pp. 408–410.

Scott, S.

S. Scott, “Optical interconnects in future HPC systems,” in Proc. Opt. Fiber Commun. Conf. Expo. Nat. Fiber Opt. Eng. Conf., 2011, Paper OWH5.

Sekiguchi, S.

T. Akiyama, S. Tanaka, and S. Sekiguchi, “A novel ultralow power consumption transmitter having a laser injection-locked by a silicon microring modulator,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper M.1.C.1.

Shiraishi, T.

T. Shiraishi, H. Oku, Y. Tsunoda, and S. Ide, “A 4 × 25.8-Gbps -13.7-dBm sensitivity optical receiver with <0.3 dB crosstalk penalty for 100-G short-reach application,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2016, Paper Th4D.

Tanaka, S.

S. Tanakaet al., “Ultra-low-power (1.59 mW/Gbps), 56-Gbps PAM4 operation of Si photonic transmitter integrating segmented PIN Mach-Zehnder modulator and 28-nm CMOS driver,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper Th.1.C.1.

T. Akiyama, S. Tanaka, and S. Sekiguchi, “A novel ultralow power consumption transmitter having a laser injection-locked by a silicon microring modulator,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper M.1.C.1.

Tanaka, Y.

M. Nishizawa, N. Hatori, Y. Tanaka, M. Kurihara, and K. Kurata, “Packaging of 16ch (4ch × 4) integrated light sources with laser diode arrays on silicon platform,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

N. Hatori, M. Kurihara, M. Nishizawa, Y. Tanaka, and K. Kurata, “A multi-channel light source on silicon substrate by flip-chip bonding,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

Tsunoda, Y.

T. Shiraishi, H. Oku, Y. Tsunoda, and S. Ide, “A 4 × 25.8-Gbps -13.7-dBm sensitivity optical receiver with <0.3 dB crosstalk penalty for 100-G short-reach application,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2016, Paper Th4D.

Verbrugghe, J.

J. Verbruggheet al., “Multichannel 25 Gb/s low-Power Driver and transimpedance amplifier Integrated Circuits for 100 Gb/s Optical Links,” J. Lightw. Technol., vol. 32, no. 16, pp. 2877–2885, Aug. 2014.

IEEE J. Solid-State Circuit, (1)

E. J. Fluhret al., “The 12-core POWER8 processor With 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking,” IEEE J. Solid-State Circuit, vol. 50, no. 1, pp. 10–23, 2015.

IEEE Trans. Adv. Packag. (1)

D. G. Kamet al., “Is 25 Gb/s on-board signaling viable?” IEEE Trans. Adv. Packag., vol. 32, no. 2, pp. 328–344, 2009.

J. Lightw. Technol. (2)

G. Denoyeret al., “Hybrid silicon photonic circuits and transceiver for 50 Gb/s NRZ transmission over single-mode fiber,” J. Lightw. Technol., vol. 33, no. 6, pp. 1247–1254, 2015.

J. Verbruggheet al., “Multichannel 25 Gb/s low-Power Driver and transimpedance amplifier Integrated Circuits for 100 Gb/s Optical Links,” J. Lightw. Technol., vol. 32, no. 16, pp. 2877–2885, Aug. 2014.

Other (13)

S. Tanakaet al., “Ultra-low-power (1.59 mW/Gbps), 56-Gbps PAM4 operation of Si photonic transmitter integrating segmented PIN Mach-Zehnder modulator and 28-nm CMOS driver,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper Th.1.C.1.

T. Akiyama, S. Tanaka, and S. Sekiguchi, “A novel ultralow power consumption transmitter having a laser injection-locked by a silicon microring modulator,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper M.1.C.1.

P. De Dobbelaere, “Silicon photonics transceivers for hyper‐scale datacenters: Deployment and roadmap,” 2016. [Online]. Available: http://www.phoxtrot.eu/wp-content/uploads/2017/01/ECOC-2016-Peter-De-Dobbelaere.pdf

M. Rakowskiet al., “A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver,” in Proc. Int. Solid-State Circuits Conf., 2015, pp. 408–410.

“Fujitsu supercomputer PRIMEHPC FX 100 evolution to the next generation,” Fujitsu, Ltd., White Paper.2014. [Online]. Available: https://pdfs.semanticscholar.org/961e/6b74f0f419838d8fd9cebf968e99603a6d4d.pdf

A. Hayakawaet al., “A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2015, Paper Th1G.2.

T. Aokiet al., “Low Crosstalk Simultaneous 12 ch × 25 Gb/s operation of high-density silicon photonics multichannel receiver,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2017, Paper Th1G.2.

T. Aokiet al., “Low crosstalk simultaneous 16-channel × 25 Gb/s operation of high density silicon photonics optical transceiver,” in Proc. Eur. Conf. Opt. Commun., 2017, Paper Tu.1.C.3.

N. Hatori, M. Kurihara, M. Nishizawa, Y. Tanaka, and K. Kurata, “A multi-channel light source on silicon substrate by flip-chip bonding,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

M. Nishizawa, N. Hatori, Y. Tanaka, M. Kurihara, and K. Kurata, “Packaging of 16ch (4ch × 4) integrated light sources with laser diode arrays on silicon platform,” in Proc. 6th Int. Sym. Photon. Electron. Conv., 2016.

Y. Chenet al., “A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI,” in Proc. IEEE Int. Solid-State Circuits Conf., 2015, pp. 402–404.

T. Shiraishi, H. Oku, Y. Tsunoda, and S. Ide, “A 4 × 25.8-Gbps -13.7-dBm sensitivity optical receiver with <0.3 dB crosstalk penalty for 100-G short-reach application,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2016, Paper Th4D.

S. Scott, “Optical interconnects in future HPC systems,” in Proc. Opt. Fiber Commun. Conf. Expo. Nat. Fiber Opt. Eng. Conf., 2011, Paper OWH5.

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