Abstract

A precise device model of a silicon forward-biased PIN phase shifter was developed to realize a codesign of an integrated multilevel optical transmitter combining a compact silicon-based Mach–Zehnder modulator (MZM) and a low-power CMOS driver circuit by utilizing SPICE simulation. Both electric and optical responses of the PIN phase shifter were carefully investigated at various bias conditions and temperatures in order to build a SPICE device model that precisely emulates a highly nonlinear electric-to-optical (EO) response of the PIN phase shifter. The validity of the developed model was assessed for a dc response, small-signal RF electric, and optical responses, and also for large-signal EO responses. The simulation outputs exhibited very good agreement with the responses measured at each operation condition. Using this PIN phase shifter model, we designed a multilevel optical transmitter integrating a 750-μm long silicon PIN-based MZM with a 28-nm CMOS driver circuit via passive RC circuit equalizers. The SPICE simulation demonstrated the feasibility of the integrated transmitter for 56 Gbps PAM4 operation with a very high energy efficiency: 1.2 mW/Gbps.

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2016 (3)

B. Wanget al., “A Compact verilog-A model of silicon carrier-injection ring modulators for optical interconnect transceiver circuit design,” J. Lightw. Technol., vol. 34, no. 12, pp. 2996–3005, 2016.

P. Ritoet al., “A monolithically integrated segmented linear driver and modulator in EPIC 0.25-μm SiGe:C BiCMOS platform,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 2, pp. 456–4572, 2016.

T. N. Huynhet al., “Flexible transmitter employing silicon-segmented Mach–Zehnder modulator with 32-nm CMOS distributed driver,” IEEE/OSA J. Lightw. Technol., vol. 34, no. 22, pp. 5129–5136, 2016.

2015 (2)

T. Babaet al., “25-Gb/s broadband silicon modulator with 0.31-V·cm VπL based on forward-biased PIN diodes embedded with passive equalizer,” Opt. Express, vol. 23 no. 26, pp. 32950–32960, 2015.

D. M. Gillet al., “Demonstration of a high extinction ratio monolithic CMOS integrated nanophotonic transmitter and 16 Gb/s optical lsink,” IEEE J. Sel. Top. Quantum Electron. vol. 21 no. 4, pp. 212–222, 2015.

2014 (1)

2013 (1)

S. Akiyamaet al., “Compact PIN-diode-based silicon modulator using side-wall-grating waveguide,” IEEE J. Sel. Top. Quantum Electron. vol. 19 no. 6, pp. 74–84, 2013.

2006 (1)

W. Zhaoet al., “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Trans. Electron. Devices, vol. 53, no. 11, pp. 2816–2823, 2006.

1987 (1)

R. Sorefet al., “Electrooptical effects in silicon,” IEEE J.Quantum Electron. vol. 23 no. 1, pp. 123–129, 1987.

Akiyama, S.

S. Akiyamaet al., “Compact PIN-diode-based silicon modulator using side-wall-grating waveguide,” IEEE J. Sel. Top. Quantum Electron. vol. 19 no. 6, pp. 74–84, 2013.

Baba, T.

Chagnon, M.

Gill, D. M.

D. M. Gillet al., “Demonstration of a high extinction ratio monolithic CMOS integrated nanophotonic transmitter and 16 Gb/s optical lsink,” IEEE J. Sel. Top. Quantum Electron. vol. 21 no. 4, pp. 212–222, 2015.

Hayakawa, A.

A. Hayakawaet al., “A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects,” in Proc. Opt. Fiber. Commun. Conf., 2015, Paper Th1G.2.

Huynh, T. N.

T. N. Huynhet al., “Flexible transmitter employing silicon-segmented Mach–Zehnder modulator with 32-nm CMOS distributed driver,” IEEE/OSA J. Lightw. Technol., vol. 34, no. 22, pp. 5129–5136, 2016.

Kato, T.

T. Katoet al., “10-Gb/s – 80-km operation of full C-band InP MZ modulator with linear-accelerator-type tiny in-line centipede electrode structure directly driven by logic IC of 90-nm CMOS process,” in Proc. Opt. Fiber. Commun. Conf., 2011, Paper OThP4.

Mazzini, M.

M. Mazziniet al., “25 GBaud PAM-4 error free transmission over both single mode fiber and multimode fiber in a QSFP form factor based on silicon photonics,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2015, Paper Th.5.B.3.

Narasimha, A.

A. Narasimhaet al., “An ultra low power CMOS photonics technology platform for H/S optoelectronic transceivers at less than $1 per Gbps,” in Proc. Opt. Fiber. Commun. Conf., 2010, Paper OMV4.

Rakowski, M.

M. Rakowskiet al., “A 4 × 20 Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver,” in Proc. IEEE ISSCC Dig. Tech. Papers, 2015, pp. 408–410.

Rito, P.

P. Ritoet al., “A monolithically integrated segmented linear driver and modulator in EPIC 0.25-μm SiGe:C BiCMOS platform,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 2, pp. 456–4572, 2016.

Soref, R.

R. Sorefet al., “Electrooptical effects in silicon,” IEEE J.Quantum Electron. vol. 23 no. 1, pp. 123–129, 1987.

Tanaka, S.

S. Tanakaet al., “Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 operation of Si photonic transmitter integrating segmented PIN Mach-Zehnder modulator and 28-nm CMOS driver,” in Proc Eur. Conf. Opt. Commun., Gothenburg, Sweden, 2017, Th. 1. C. 1.

Wang, B.

B. Wanget al., “A Compact verilog-A model of silicon carrier-injection ring modulators for optical interconnect transceiver circuit design,” J. Lightw. Technol., vol. 34, no. 12, pp. 2996–3005, 2016.

Webster, M.

M. Websteret al., “Low-Power MOS-Capacitor based silicon photonic modulators and CMOS drivers,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2015, Paper W4H.3.

Wu, X.

X. Wuet al., “A 20 Gb/s NRZ/PAM-4 1V transmitter in 40 nm CMOS driving a Si-photonic modulator in 0.13 μm CMOS,” in Proc. IEEE ISSCC Dig. Tech. Papers, 2013, pp. 128–130.

Xiong, C.

C. Xionget al., “A monolithic 56 Gb/s CMOS integrated nanophotonic PAM-4 transmitter,” in Proc. IEEE Optical Interconnect Conf., 2015, Paper MC3.

Yashiki, K.

K. Yashikiet al., “5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF,” in Proc. Opt. Fiber. Commun. Conf., 2015, Paper Th1G.1.

Zhao, W.

W. Zhaoet al., “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Trans. Electron. Devices, vol. 53, no. 11, pp. 2816–2823, 2006.

400 Gb/s Ethernet Task Force (1)

IEEE 802.3bs 200 Gb/s and 400 Gb/s Ethernet Task Force.

IEEE J. Sel. Top. Quantum Electron. (2)

D. M. Gillet al., “Demonstration of a high extinction ratio monolithic CMOS integrated nanophotonic transmitter and 16 Gb/s optical lsink,” IEEE J. Sel. Top. Quantum Electron. vol. 21 no. 4, pp. 212–222, 2015.

S. Akiyamaet al., “Compact PIN-diode-based silicon modulator using side-wall-grating waveguide,” IEEE J. Sel. Top. Quantum Electron. vol. 19 no. 6, pp. 74–84, 2013.

IEEE J.Quantum Electron. (1)

R. Sorefet al., “Electrooptical effects in silicon,” IEEE J.Quantum Electron. vol. 23 no. 1, pp. 123–129, 1987.

IEEE Trans. Electron. Devices (1)

W. Zhaoet al., “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Trans. Electron. Devices, vol. 53, no. 11, pp. 2816–2823, 2006.

IEEE Trans. Microw. Theory Tech. (1)

P. Ritoet al., “A monolithically integrated segmented linear driver and modulator in EPIC 0.25-μm SiGe:C BiCMOS platform,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 2, pp. 456–4572, 2016.

IEEE/OSA J. Lightw. Technol. (1)

T. N. Huynhet al., “Flexible transmitter employing silicon-segmented Mach–Zehnder modulator with 32-nm CMOS distributed driver,” IEEE/OSA J. Lightw. Technol., vol. 34, no. 22, pp. 5129–5136, 2016.

J. Lightw. Technol. (1)

B. Wanget al., “A Compact verilog-A model of silicon carrier-injection ring modulators for optical interconnect transceiver circuit design,” J. Lightw. Technol., vol. 34, no. 12, pp. 2996–3005, 2016.

Opt. Express (2)

Other (11)

A. Narasimhaet al., “An ultra low power CMOS photonics technology platform for H/S optoelectronic transceivers at less than $1 per Gbps,” in Proc. Opt. Fiber. Commun. Conf., 2010, Paper OMV4.

T. Katoet al., “10-Gb/s – 80-km operation of full C-band InP MZ modulator with linear-accelerator-type tiny in-line centipede electrode structure directly driven by logic IC of 90-nm CMOS process,” in Proc. Opt. Fiber. Commun. Conf., 2011, Paper OThP4.

[Online]. Available: http://ptm.asu.edu/

S. Tanakaet al., “Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 operation of Si photonic transmitter integrating segmented PIN Mach-Zehnder modulator and 28-nm CMOS driver,” in Proc Eur. Conf. Opt. Commun., Gothenburg, Sweden, 2017, Th. 1. C. 1.

X. Wuet al., “A 20 Gb/s NRZ/PAM-4 1V transmitter in 40 nm CMOS driving a Si-photonic modulator in 0.13 μm CMOS,” in Proc. IEEE ISSCC Dig. Tech. Papers, 2013, pp. 128–130.

C. Xionget al., “A monolithic 56 Gb/s CMOS integrated nanophotonic PAM-4 transmitter,” in Proc. IEEE Optical Interconnect Conf., 2015, Paper MC3.

M. Rakowskiet al., “A 4 × 20 Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver,” in Proc. IEEE ISSCC Dig. Tech. Papers, 2015, pp. 408–410.

A. Hayakawaet al., “A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects,” in Proc. Opt. Fiber. Commun. Conf., 2015, Paper Th1G.2.

K. Yashikiet al., “5 mW/Gbps hybrid-integrated Si-photonics-based optical I/O cores and their 25-Gbps/ch error-free operation with over 300-m MMF,” in Proc. Opt. Fiber. Commun. Conf., 2015, Paper Th1G.1.

M. Websteret al., “Low-Power MOS-Capacitor based silicon photonic modulators and CMOS drivers,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2015, Paper W4H.3.

M. Mazziniet al., “25 GBaud PAM-4 error free transmission over both single mode fiber and multimode fiber in a QSFP form factor based on silicon photonics,” in Proc. Opt. Fiber Commun. Conf. Exhib., 2015, Paper Th.5.B.3.

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