Abstract

Passive optical interconnection network (OIN) plays a key role in optical Network-on-Chip (ONoC) architecture. Existing passive OINs based on wavelength division multiplexing (WDM) are popularly employed. However, the scalability of these passive OINs is limited by the number of wavelengths and large insertion loss induced by the waveguide crossings. In this paper, we propose a novel Passive OIN based on two-layer architecture, POINT, for ONoC architecture. POINT leverages space division multiplexing (SDM) to assist WDM in eliminating blocking. The inter-layer communication in POINT relies on the inter-layer coupler, which contributes to reduce crossing losses. POINT features a modular and scalable design, in which the proposed SDM-based cell (SBC) is used as the basic building block to construct POINT with efficient wavelength assignment. Furthermore, SBCs of different sizes provide different options for constructing POINT. Comparisons with existing passive OINs confirm that POINT can provide an optimal choice with the balance between the number of wavelengths, area overhead, and insertion loss for the same size.

© 2014 IEEE

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  1. D. Xiang, Y. Zhang, " Cost-effective power-aware core testing in NoCs based on a new unicast-based mul-ticast scheme," IEEE Trans. Comput.-Aided Design 30, 135-146 (2011).
  2. R. Min, R. Ji, Q. Chen, L. Zhang, L. Yang, "A universal method for constructing N-port nonblocking optical router for photonic networks -on-chip," J. Lightw. Technol. 30, 3736 -3741 (2012).
  3. G. Chen, H. Chen, M. Haurylau, N. Nelson, D. Albonesi, P. Fauchet, E. Friedman, "On-chip copper-based vs. optical interconnects: Delay uncertainty, latency, power, and bandwidth density comparative predictions," Proc. IEEE Int. Interconnect Technol. Conf. (2006) pp. 39 -41.
  4. K. Mo, Y. Ye, X. Wu, W. Zhang, W. Liu, J. Xu, "A hierarchical hybrid optical-electronic network-on-chip ," Proc. IEEE Comput. Soc. Annu. Symp. VLSI (2010) pp. 327-332.
  5. C. Lea, B. Lin, "A new approach to the wavelength non-uniformity problem of silicon photon IC microrings," J. Lightw. Technol. 29, 2552-2559 (2011).
  6. A. Biberman, B. Lee, N. Sherwood-Droz, M. Lipson, K. Bergman, "Broadband operation of nanophotonic router for silicon photonic networks-on-chip," IEEE Photon. Technol. Lett. 22, 926-928 (2010).
  7. Y. Xie, J. Xu, J. Zhang, Z. Wu, G. Xia, "Crosstalk noise analysis and optimization in 5 × 5 hitless silicon-based optical router for optical networks-on-chip (ONoC) ," J. Lightw. Technol. 30, 198-203 (2012).
  8. A. Atef, I. O’Connor, W. Heirman, "Performance evaluation for passive-type optical network-on-chip," Proc. IEEE Int. Symp. Rapid Syst. Prototyping (2010) pp. 1-7.
  9. A. Shacham, K. Bergman, L. P. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors," IEEE Trans. Comput. 57 , 1246-1260 (2008).
  10. Z. Li, M. Mohamed, X. Chen, H. Zhou, A. Mickelson, L. Shang, M. Vachharajani, "Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication," J. Emerging Technol. Comput. Syst. 7, 8 (2011).
  11. H. Gu, K. Mo, J. Xu, W. Zhang, "A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems–on chip," Proc. Int. Symp. VLSI (2009) pp. 19-24.
  12. M. Brière, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Gaffiot, I. O’Connor, "System level assessment of an optical NoC in an MPSoC platform," Proc. Design, Autom. Test Eur. Conf. Exhib. (2007) pp. 1 -6.
  13. X. Tan, M. Yang, L. Zhang, Y. Jiang, J. Yang, "A generic optical router design for photonic network-on-chips," IEEE J. Lightw. Technol. 30, 368-376 (2012).
  14. K. Preston, N. Sherwood-Droz, J. Levy, M. Lipson, "Performance guidelines for WDM interconnects based on silicon microring resonators ," Proc. Conf. Lasers Electro-Opt. (2011) pp. 1-2.
  15. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, K. Asanovic, "Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics," IEEE Micro 29 , 8-21 (2009).
  16. S. Beux, J. Trajkovic, I. O’Connor, G. Nicolescu, G. Bois, P. Paulin, "Optical ring network-on-chip (ORNoC): Architecture and design methodology," Proc. Des., Autom. Test Eur. Conf. Exhib. (2011) pp. 1-6.
  17. A. Biberman, N. Sherwood-Droz, X. Zhu, K Preston, G. Hendry, J. Levy, J. Chan, H. Wang, M. Lipson, K. Bergman, "Photonic network-on-chip architecture using 3D integration," Proc. SPIE 7942, 79420M-1 ( 2011).
  18. X. Zhang, A. Louri, " A multilayer nanophotonic interconnection network for on-chip many-core communications," Proc. 47th Des. Autom. Conf. (2010) pp. 156-161.
  19. N. Sherwood-Droz, H. Wang, L. Chen, B. Lee, A. Biberman, K. Bergman, M. Lipson, "Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC) ," Opt. Exp. 16, 15915-15922 (2008).
  20. R. Dokania, A. Apsel, " Analysis of challenges for on-chip optical interconnects," Proc.19th ACM Great Lakes Symp. VLSI (2009) pp. 275-280.
  21. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. Beausoleil, J. Ahn, "Corona: System implications of emerging nanophotonic technology," Proc. 35th Int. Symp. Comput. Archit. ( 2008) pp. 153-164.

2012 (3)

R. Min, R. Ji, Q. Chen, L. Zhang, L. Yang, "A universal method for constructing N-port nonblocking optical router for photonic networks -on-chip," J. Lightw. Technol. 30, 3736 -3741 (2012).

Y. Xie, J. Xu, J. Zhang, Z. Wu, G. Xia, "Crosstalk noise analysis and optimization in 5 × 5 hitless silicon-based optical router for optical networks-on-chip (ONoC) ," J. Lightw. Technol. 30, 198-203 (2012).

X. Tan, M. Yang, L. Zhang, Y. Jiang, J. Yang, "A generic optical router design for photonic network-on-chips," IEEE J. Lightw. Technol. 30, 368-376 (2012).

2011 (3)

D. Xiang, Y. Zhang, " Cost-effective power-aware core testing in NoCs based on a new unicast-based mul-ticast scheme," IEEE Trans. Comput.-Aided Design 30, 135-146 (2011).

Z. Li, M. Mohamed, X. Chen, H. Zhou, A. Mickelson, L. Shang, M. Vachharajani, "Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication," J. Emerging Technol. Comput. Syst. 7, 8 (2011).

C. Lea, B. Lin, "A new approach to the wavelength non-uniformity problem of silicon photon IC microrings," J. Lightw. Technol. 29, 2552-2559 (2011).

2010 (1)

A. Biberman, B. Lee, N. Sherwood-Droz, M. Lipson, K. Bergman, "Broadband operation of nanophotonic router for silicon photonic networks-on-chip," IEEE Photon. Technol. Lett. 22, 926-928 (2010).

2009 (1)

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, K. Asanovic, "Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics," IEEE Micro 29 , 8-21 (2009).

2008 (2)

N. Sherwood-Droz, H. Wang, L. Chen, B. Lee, A. Biberman, K. Bergman, M. Lipson, "Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC) ," Opt. Exp. 16, 15915-15922 (2008).

A. Shacham, K. Bergman, L. P. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors," IEEE Trans. Comput. 57 , 1246-1260 (2008).

J. Lightw. Technol. (1)

C. Lea, B. Lin, "A new approach to the wavelength non-uniformity problem of silicon photon IC microrings," J. Lightw. Technol. 29, 2552-2559 (2011).

IEEE J. Lightw. Technol. (1)

X. Tan, M. Yang, L. Zhang, Y. Jiang, J. Yang, "A generic optical router design for photonic network-on-chips," IEEE J. Lightw. Technol. 30, 368-376 (2012).

IEEE Micro (1)

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, K. Asanovic, "Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics," IEEE Micro 29 , 8-21 (2009).

IEEE Photon. Technol. Lett. (1)

A. Biberman, B. Lee, N. Sherwood-Droz, M. Lipson, K. Bergman, "Broadband operation of nanophotonic router for silicon photonic networks-on-chip," IEEE Photon. Technol. Lett. 22, 926-928 (2010).

IEEE Trans. Comput. (1)

A. Shacham, K. Bergman, L. P. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors," IEEE Trans. Comput. 57 , 1246-1260 (2008).

IEEE Trans. Comput.-Aided Design (1)

D. Xiang, Y. Zhang, " Cost-effective power-aware core testing in NoCs based on a new unicast-based mul-ticast scheme," IEEE Trans. Comput.-Aided Design 30, 135-146 (2011).

J. Emerging Technol. Comput. Syst. (1)

Z. Li, M. Mohamed, X. Chen, H. Zhou, A. Mickelson, L. Shang, M. Vachharajani, "Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication," J. Emerging Technol. Comput. Syst. 7, 8 (2011).

J. Lightw. Technol. (2)

R. Min, R. Ji, Q. Chen, L. Zhang, L. Yang, "A universal method for constructing N-port nonblocking optical router for photonic networks -on-chip," J. Lightw. Technol. 30, 3736 -3741 (2012).

Y. Xie, J. Xu, J. Zhang, Z. Wu, G. Xia, "Crosstalk noise analysis and optimization in 5 × 5 hitless silicon-based optical router for optical networks-on-chip (ONoC) ," J. Lightw. Technol. 30, 198-203 (2012).

Opt. Exp. (1)

N. Sherwood-Droz, H. Wang, L. Chen, B. Lee, A. Biberman, K. Bergman, M. Lipson, "Optical 4 × 4 hitless silicon router for optical networks-on-chip (NoC) ," Opt. Exp. 16, 15915-15922 (2008).

Proc. SPIE (1)

A. Biberman, N. Sherwood-Droz, X. Zhu, K Preston, G. Hendry, J. Levy, J. Chan, H. Wang, M. Lipson, K. Bergman, "Photonic network-on-chip architecture using 3D integration," Proc. SPIE 7942, 79420M-1 ( 2011).

Other (10)

X. Zhang, A. Louri, " A multilayer nanophotonic interconnection network for on-chip many-core communications," Proc. 47th Des. Autom. Conf. (2010) pp. 156-161.

R. Dokania, A. Apsel, " Analysis of challenges for on-chip optical interconnects," Proc.19th ACM Great Lakes Symp. VLSI (2009) pp. 275-280.

D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. Beausoleil, J. Ahn, "Corona: System implications of emerging nanophotonic technology," Proc. 35th Int. Symp. Comput. Archit. ( 2008) pp. 153-164.

A. Atef, I. O’Connor, W. Heirman, "Performance evaluation for passive-type optical network-on-chip," Proc. IEEE Int. Symp. Rapid Syst. Prototyping (2010) pp. 1-7.

G. Chen, H. Chen, M. Haurylau, N. Nelson, D. Albonesi, P. Fauchet, E. Friedman, "On-chip copper-based vs. optical interconnects: Delay uncertainty, latency, power, and bandwidth density comparative predictions," Proc. IEEE Int. Interconnect Technol. Conf. (2006) pp. 39 -41.

K. Mo, Y. Ye, X. Wu, W. Zhang, W. Liu, J. Xu, "A hierarchical hybrid optical-electronic network-on-chip ," Proc. IEEE Comput. Soc. Annu. Symp. VLSI (2010) pp. 327-332.

H. Gu, K. Mo, J. Xu, W. Zhang, "A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems–on chip," Proc. Int. Symp. VLSI (2009) pp. 19-24.

M. Brière, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Gaffiot, I. O’Connor, "System level assessment of an optical NoC in an MPSoC platform," Proc. Design, Autom. Test Eur. Conf. Exhib. (2007) pp. 1 -6.

S. Beux, J. Trajkovic, I. O’Connor, G. Nicolescu, G. Bois, P. Paulin, "Optical ring network-on-chip (ORNoC): Architecture and design methodology," Proc. Des., Autom. Test Eur. Conf. Exhib. (2011) pp. 1-6.

K. Preston, N. Sherwood-Droz, J. Levy, M. Lipson, "Performance guidelines for WDM interconnects based on silicon microring resonators ," Proc. Conf. Lasers Electro-Opt. (2011) pp. 1-2.

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