Abstract
Chip-scale photonic interconnection networks have emerged as a promising
technology solution that can address many of the scalability challenges facing the
communication networks in next-generation high-performance multicore processors.
Photonic interconnects can offer significantly higher bandwidth density, lower
latencies, and better energy efficiency. Even though photonics exhibits these inherent
advantages over electronics, the network designs that can successfully leverage these
benefits cannot be straightforwardly extracted from typical electronic network
methodologies and must consider the many unique physical-layer constraints of optical
technologies. We conduct an architectural exploration of four chip-scale photonic
interconnection networks in a novel simulation environment, measuring insertion loss,
crosstalk, and power. We also explain and demonstrate the impact of these physical-layer
metrics on the scalability, performance, and realizability of each design.
© 2010 IEEE
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