Abstract

This paper compares two burst-mode clock and data recovery (BM-CDR) techniques suitable for bursty upstream data transmission, namely a gated voltage controlled oscillator (GVCO) and an oversampling clock phase alignment (CPA). Numeric models were deduced with timing jitter and duty cycle distortion (DCD) present in the received data. The performance of the two techniques are analyzed and compared especially in an optically amplified long-reach high-split PON (LR-PON) system. It is shown that an oversampling CPA exhibits a large DCD tolerance and better jitter rejection than a GVCO without line coding, resulting in high network efficiency while keeping fast bit synchronisation. This makes the oversampling CPA technique the best option for the proposed network.

© 2009 IEEE

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  1. C.-H. Lee, W. V. Sorin, "Fiber to the home using a PON infrastructure," J. Lightw. Technol. 24, 4568-4583 (2006).
  2. R. Davey, J. Kani, "Options for future optical access networks," IEEE Comm. Mag. 44, 50-56 (2006).
  3. P. D. Townsend, G. Talli, "Long reach passive optical networks," Proc. IEEE LEOS Annual Meeting Lake Buena VistaFL () ThW1.
  4. X.-Z. Qiu, P. Ossieur, "Development of GPON upstream physical-media-dependent prototypes," J. Lightw. Technol. 22, 2498-2508 (2004).
  5. M. Banu, A. Dunlop, "A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (1993) pp. 102-103.
  6. A. Li, J. Faucher, "Burst-mode clock and data recovery in optical multiaccess networks using broadband PLLs," IEEE Technol. Lett. 18, 73-75 (2006).
  7. W. Fisher, A. Dunlop, "150/60 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (1995) pp. 44-46.
  8. P. Han, W. Choi, "1 Gbps gated-oscillator burst mode CDR with half-rate clock recovery," J. Semicond. Technol. Sci. 4, (2004).
  9. K. Nishimura, M. Nogawa, "A 10 Gb/s burst-mode CDR IC in 0.13 $\mu{\rm m}$ CMOS," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (2005) pp. 228-229.
  10. C.-F. Liang, S.-C. Hwu, "A 10 Gbps burs-mode CDR circuit in 0.18 um CMOS," Proc. IEEE Custom Integrated Circuits Conf. (CICC) (2006) pp. 228-229.
  11. J. Terada, K. Nishimura, "A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance," Proc. Eur. Conf. Optical Commun. (ECOC) (2007) paper 6.6.7.
  12. C.-F. Liang, S.-I. Liu, "A 20/10/5/2.5 Gb/s power-scaling burst-mode CDR circuit using GVCO/Div2/DFF tri-mode cells," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (2008) paper 11.3.
  13. C. Eldering, F. Herrerias-Martin, "Digital burst mode clock recovery technique for fiber-optic systems," J. Lightw. Technol. 12, 271-279 (1994).
  14. R. Farjad-Rad, C.-K. Yang, "A 0.5 $\mu{\rm m}$ CMOS 4.0 Gb/s serial link transceiver with data recovery using oversampling," IEEE J. Solid-State Circuits 33, 713-722 (1998).
  15. D. Verhulst, Y. Yi, "Upstream experiments on the Gigabit PON physical medium layer," Proc. Opt. Fibre Commun. Conf. (OFC) (2005) pp. 1-3.
  16. P. Ossieur, J. Bauwelinck, "A dual-rate burst-mode bit synchronization and data recovery circuit with fixed output clock phase," Int. J. Electron. Commun. (AEU) .
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  19. G. Talli, P. Townsend, "Hybrid DWDM-TDM long-reach PON for next-generation optical access," J. Lightw. Technol. 24, 2827-2834 (2006).
  20. H. Tagami, S. Kozaki, "A burst-mode bit-synchronization IC with large tolerance for pulse-width distortion for gigabit ethernet PON," IEEE J. Solid-State Circuits 41, 2555-2565 (2006).
  21. C.-Y. Yang, J.-M. Lin, "A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation," IEICE Trans. Electron. E90-C, 196-200 (2007).
  22. C. McKinstrie, J. Santhanam, "Gordon-Haus timing jitter in dispersion-managed systems with lumped amplification: Analytical approach," J. Opt. Soc. Am. B 19, 640-649 (2002).

2007 (1)

C.-Y. Yang, J.-M. Lin, "A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation," IEICE Trans. Electron. E90-C, 196-200 (2007).

2006 (5)

C.-H. Lee, W. V. Sorin, "Fiber to the home using a PON infrastructure," J. Lightw. Technol. 24, 4568-4583 (2006).

R. Davey, J. Kani, "Options for future optical access networks," IEEE Comm. Mag. 44, 50-56 (2006).

A. Li, J. Faucher, "Burst-mode clock and data recovery in optical multiaccess networks using broadband PLLs," IEEE Technol. Lett. 18, 73-75 (2006).

G. Talli, P. Townsend, "Hybrid DWDM-TDM long-reach PON for next-generation optical access," J. Lightw. Technol. 24, 2827-2834 (2006).

H. Tagami, S. Kozaki, "A burst-mode bit-synchronization IC with large tolerance for pulse-width distortion for gigabit ethernet PON," IEEE J. Solid-State Circuits 41, 2555-2565 (2006).

2004 (2)

P. Han, W. Choi, "1 Gbps gated-oscillator burst mode CDR with half-rate clock recovery," J. Semicond. Technol. Sci. 4, (2004).

X.-Z. Qiu, P. Ossieur, "Development of GPON upstream physical-media-dependent prototypes," J. Lightw. Technol. 22, 2498-2508 (2004).

2002 (1)

2000 (1)

E. Forestieri, "Evaluating the error probability in lightwave systems with chromatic dispersion, arbitrary pulse shape and pre- and postdetection filtering," J. Lightw. Technol. 18, 1493-1503 (2000).

1998 (2)

H. A. Haus, "The noise figure of optical amplifiers," IEEE Photon. Technol. Lett. 10, 1602-1604 (1998).

R. Farjad-Rad, C.-K. Yang, "A 0.5 $\mu{\rm m}$ CMOS 4.0 Gb/s serial link transceiver with data recovery using oversampling," IEEE J. Solid-State Circuits 33, 713-722 (1998).

1994 (1)

C. Eldering, F. Herrerias-Martin, "Digital burst mode clock recovery technique for fiber-optic systems," J. Lightw. Technol. 12, 271-279 (1994).

IEEE Comm. Mag. (1)

R. Davey, J. Kani, "Options for future optical access networks," IEEE Comm. Mag. 44, 50-56 (2006).

IEEE J. Solid-State Circuits (2)

R. Farjad-Rad, C.-K. Yang, "A 0.5 $\mu{\rm m}$ CMOS 4.0 Gb/s serial link transceiver with data recovery using oversampling," IEEE J. Solid-State Circuits 33, 713-722 (1998).

H. Tagami, S. Kozaki, "A burst-mode bit-synchronization IC with large tolerance for pulse-width distortion for gigabit ethernet PON," IEEE J. Solid-State Circuits 41, 2555-2565 (2006).

IEEE Photon. Technol. Lett. (1)

H. A. Haus, "The noise figure of optical amplifiers," IEEE Photon. Technol. Lett. 10, 1602-1604 (1998).

IEEE Technol. Lett. (1)

A. Li, J. Faucher, "Burst-mode clock and data recovery in optical multiaccess networks using broadband PLLs," IEEE Technol. Lett. 18, 73-75 (2006).

IEICE Trans. Electron. (1)

C.-Y. Yang, J.-M. Lin, "A 1.25-Gb/s burst-mode half-rate clock and data recovery circuit using realigned oscillation," IEICE Trans. Electron. E90-C, 196-200 (2007).

Int. J. Electron. Commun. (AEU) (1)

P. Ossieur, J. Bauwelinck, "A dual-rate burst-mode bit synchronization and data recovery circuit with fixed output clock phase," Int. J. Electron. Commun. (AEU) .

J. Lightw. Technol. (3)

C. Eldering, F. Herrerias-Martin, "Digital burst mode clock recovery technique for fiber-optic systems," J. Lightw. Technol. 12, 271-279 (1994).

X.-Z. Qiu, P. Ossieur, "Development of GPON upstream physical-media-dependent prototypes," J. Lightw. Technol. 22, 2498-2508 (2004).

G. Talli, P. Townsend, "Hybrid DWDM-TDM long-reach PON for next-generation optical access," J. Lightw. Technol. 24, 2827-2834 (2006).

J. Lightw. Technol. (1)

E. Forestieri, "Evaluating the error probability in lightwave systems with chromatic dispersion, arbitrary pulse shape and pre- and postdetection filtering," J. Lightw. Technol. 18, 1493-1503 (2000).

J. Lightw. Technol. (1)

C.-H. Lee, W. V. Sorin, "Fiber to the home using a PON infrastructure," J. Lightw. Technol. 24, 4568-4583 (2006).

J. Opt. Soc. Am. B (1)

J. Semicond. Technol. Sci. (1)

P. Han, W. Choi, "1 Gbps gated-oscillator burst mode CDR with half-rate clock recovery," J. Semicond. Technol. Sci. 4, (2004).

Other (8)

K. Nishimura, M. Nogawa, "A 10 Gb/s burst-mode CDR IC in 0.13 $\mu{\rm m}$ CMOS," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (2005) pp. 228-229.

C.-F. Liang, S.-C. Hwu, "A 10 Gbps burs-mode CDR circuit in 0.18 um CMOS," Proc. IEEE Custom Integrated Circuits Conf. (CICC) (2006) pp. 228-229.

J. Terada, K. Nishimura, "A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance," Proc. Eur. Conf. Optical Commun. (ECOC) (2007) paper 6.6.7.

C.-F. Liang, S.-I. Liu, "A 20/10/5/2.5 Gb/s power-scaling burst-mode CDR circuit using GVCO/Div2/DFF tri-mode cells," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (2008) paper 11.3.

M. Banu, A. Dunlop, "A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (1993) pp. 102-103.

P. D. Townsend, G. Talli, "Long reach passive optical networks," Proc. IEEE LEOS Annual Meeting Lake Buena VistaFL () ThW1.

W. Fisher, A. Dunlop, "150/60 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection," Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) (1995) pp. 44-46.

D. Verhulst, Y. Yi, "Upstream experiments on the Gigabit PON physical medium layer," Proc. Opt. Fibre Commun. Conf. (OFC) (2005) pp. 1-3.

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