Abstract

We propose a novel structure of a mode (de)multiplexer that realizes an on-chip (de)multiplexing function in a two-step process consisting of a bridged coupler and an oval mode converter. According to the two-step principle, we design and fabricate a three-mode (TE0, TE2, and TE4) (de)multiplexer with the standard silicon-on-isolator (SOI) technology. The measured crosstalk of the device is lower than −22.0 dB, −19.0 dB, and −16.0 dB for TE0, TE2, and TE4 modes, respectively, for wavelengths ranging from 1525 to 1585 nm. The device is tested in both single-wavelength and wavelength-division multiplexing (WDM) systems with 128 Gb/s (32 Gbaud) 16-ary quadrature amplitude modulation signals. We experimentally demonstrate 96-channel ( ${\text{32}}-{\text{wavelength}}\times {\text{3}}-{\text{mode}}$ ) on-chip WDM and mode-division multiplexing (MDM) transmission. Considering a single lane bit rate of 128 Gb/s, an on-chip data capacity of ∼10 Tb/s is achieved. To our best knowledge, this paper is the first demonstration of a Terabit on-chip WDM-MDM system that shows ultrahigh bandwidth communication on a single silicon chip.

© 2018 IEEE

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