High-κ dielectric is regarded as an effective material to reduce the operating voltage of the amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs). However, the dielectric with high permittivity often has the drawbacks of inducing small conduction band offset energy and high interface trap density. Here a bilayer HfO<sub>2</sub>/SiO<sub>2</sub> gate dielectric for thin-film transistors (TFTs) is employed to address the issues. Compare to the a-IGZO TFT with solely 15 nm-thick HfO<sub>2</sub> gate dielectric, the TFT with the bilayer HfO<sub>2</sub>/SiO<sub>2</sub> (10 nm/5 nm) gate dielectric improves the subthreshold swing (SS) from 0.22 to 0.12 V/decade, the mobility from 1.4 to 7 cm<sup>2</sup>/V ⋅ s and current on–off ratio from 9 x 10<sup>6</sup> to 1.3 x 10<sup>9</sup>. Finally, Hooge's parameters (extracted from the low-frequency noise measurement) of a-IGZO TFTs were investigated to understand the defects near the channel/dielectrics interface so that the role of the thin SiO<sub>2</sub> layer can be verified. The device with bilayer HfO<sub>2</sub>/SiO<sub>2</sub> structure exhibits a value of 2 x 10<sup>-3</sup>, which is an order of magnitude lower than the one with a single HfO<sub>2</sub> layer. The Hooge's parameter of our bilayer dielectric is the lowest among the reported metal–oxide based TFTs on the glass substrate.
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