Abstract

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer technology and providing submicron (0.35 μm) LDD regions, have been analyzed. Device characteristics show negligible series resistance of the LDD region while effective drain field relief has been demonstrated by a reduced kink effect and off-current, if compared to conventional self-aligned (SA) devices. Short channel effects are also mitigated by the LDD region, while substantial reduction in the hot-carrier induced instability is found, when compared with conventional SA devices. Optimum doping dose of the LDD region has been identified to be 9 × 10<sup>12</sup> cm<sup>2</sup>.

© 2011 IEEE

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  1. H. J. In, K. H. Oh, I. Lee, D. H. Ryu, S. M. Choi, K. N. Kim, H. D. Kim, O. K. Kwon, "An advanced external compensation system for active matrix organic light-emitting diode displays with poly-Si thin-film transistor backplane," IEEE Trans. Electron Devices 57, 3012-3019 (2010).
  2. X. Guo, S. R. P. Silva, "Investigation on the current nonuniformity in current-mode TFT active-matrix display pixel circuitry," IEEE Trans. Electron Devices 52, 2379-2385 (2005).
  3. J.-C. Goh, H.-J. Chung, J. Jang, C.-H. Han, "A new pixel circuit for active matrix organic light emitting diodes," IEEE Electron Device Lett. 23, 544-546 (2002).
  4. Y.-H. Tai, Y.-H. Tai, B.-T. Chen, Y.-J. Kuo, C.-C. Tsai, K.-Y. Chiang, Y.-J. Wei, H.-C. Cheng, "A new pixel circuit for driving organic light-emitting diode with low temperature polycrystalline silicon thin-film transistors," J. Display Technol. 1, 100-104 (2005).
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  6. F. H. Wang, H. C. Lin, P. S. Shih, L. Y. Lin, H. W. Liu, "New current programmed pixel circuit for active-matrix organic light-emitting-diode displays," Proc. IEEE Int. Conf. EDSSC (2007) pp. 1151-1154.
  7. J.-H. Lee, W.-J. Nam, B.-K. Kim, H.-S. Choi, Y.-M. Ha, M.-K. Han, "A new poly-Si TFT current-mirror pixel for active matrix organic light emitting diode," IEEE Electron Device Lett. 27, 830-833 (2004).
  8. G. Fortunato, M. Cuscunà, P. Gaucci, L. Maiolo, L. Mariucci, A. Pecora, A. Valletta, "Downscaling issues in polycrystalline silicon TFTs," ECS Trans. 33, 3-22 (2010).
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  11. A. Valletta, L. Mariucci, G. Fortunato, "Hot-carrier-induced degradation of LDD polysilicon TFTs," IEEE Trans. Electron Devices 53, 43-50 (2006).
  12. A. Bonfiglietti, M. Cuscunà, A. Valletta, L. Mariucci, A. Pecora, G. Fortunato, S. D. Brotherton, J. R. Ayres, "Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration," IEEE Trans. Electron Devices 50, 2425-2433 (2003).
  13. M. Hatano, H. Akimoto, T. Sakai, "A novel self-aligned gate overlapped LDD poly-Si TFT," Proc. IEDM 97 (1997) pp. 523-526.
  14. Y. Mishima, Y. Ebiko, "Improved lifetime of poly-Si TFTs with a self-aligned gate overlapped LDD structure," IEEE Trans. Electron Devices 49, 981-985 (2002).
  15. C. Glasse, S. D. Brotherton, I. D. French, P. W. Green, C. Rowe, "Short channel LTPS TFTs made using sidewall spacer technology," Proc. Int. Workshop AMLCD 03 (2003) pp. 317.
  16. J. P. Colinge, "Reduction of kink effect in thin-film SOI MOSFET's," IEEE Electron Device Lett. 9, 97-99 (1988).
  17. M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, I. Policicchio, "Floating body effects in polysilicon thin-film transistors," IEEE Trans. Electron Devices 44, 2234-2241 (1997).
  18. S. D. Brotherton, J. R. Ayres, M. J. Trainor, "Control and analysis of leakage currents in poly-Si TFTs," J. Appl. Phys. 79, 895-904 (1996).
  19. G. Kawachi, S. Tsuboi, T. Okada, M. Mitani, M. Matsumura, "Analysis of threshold voltage of short channel polycrystalline silicon thin-film transistors fabricated on large grains," J. Appl. Phys. 100, 114507 (2006).
  20. A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M. Cuscunà, L. Maiolo, G. Fortunato, "Threshold voltage in short channel polycrystalline silicon thin film transistors: Influence of drain induced barrier lowering and floating body effects," J. Appl. Phys. 107, 074505 (2010).
  21. R. R. Troutman, "VLSI limitations from drain-induced barrier lowering," IEEE Trans. Electron Devices ED-26, 461-469 (1979).
  22. A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M. Cuscunà, L. Maiolo, G. Fortunato, S. D. Brotherton, "Role of gate oxide thickness in controlling short channel effects in polycrystalline silicon thin film transistors," Appl. Phys. Lett. 85, 033507 (2009).

2010 (3)

H. J. In, K. H. Oh, I. Lee, D. H. Ryu, S. M. Choi, K. N. Kim, H. D. Kim, O. K. Kwon, "An advanced external compensation system for active matrix organic light-emitting diode displays with poly-Si thin-film transistor backplane," IEEE Trans. Electron Devices 57, 3012-3019 (2010).

G. Fortunato, M. Cuscunà, P. Gaucci, L. Maiolo, L. Mariucci, A. Pecora, A. Valletta, "Downscaling issues in polycrystalline silicon TFTs," ECS Trans. 33, 3-22 (2010).

A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M. Cuscunà, L. Maiolo, G. Fortunato, "Threshold voltage in short channel polycrystalline silicon thin film transistors: Influence of drain induced barrier lowering and floating body effects," J. Appl. Phys. 107, 074505 (2010).

2009 (1)

A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M. Cuscunà, L. Maiolo, G. Fortunato, S. D. Brotherton, "Role of gate oxide thickness in controlling short channel effects in polycrystalline silicon thin film transistors," Appl. Phys. Lett. 85, 033507 (2009).

2006 (2)

G. Kawachi, S. Tsuboi, T. Okada, M. Mitani, M. Matsumura, "Analysis of threshold voltage of short channel polycrystalline silicon thin-film transistors fabricated on large grains," J. Appl. Phys. 100, 114507 (2006).

A. Valletta, L. Mariucci, G. Fortunato, "Hot-carrier-induced degradation of LDD polysilicon TFTs," IEEE Trans. Electron Devices 53, 43-50 (2006).

2005 (2)

X. Guo, S. R. P. Silva, "Investigation on the current nonuniformity in current-mode TFT active-matrix display pixel circuitry," IEEE Trans. Electron Devices 52, 2379-2385 (2005).

Y.-H. Tai, Y.-H. Tai, B.-T. Chen, Y.-J. Kuo, C.-C. Tsai, K.-Y. Chiang, Y.-J. Wei, H.-C. Cheng, "A new pixel circuit for driving organic light-emitting diode with low temperature polycrystalline silicon thin-film transistors," J. Display Technol. 1, 100-104 (2005).

2004 (1)

J.-H. Lee, W.-J. Nam, B.-K. Kim, H.-S. Choi, Y.-M. Ha, M.-K. Han, "A new poly-Si TFT current-mirror pixel for active matrix organic light emitting diode," IEEE Electron Device Lett. 27, 830-833 (2004).

2003 (1)

A. Bonfiglietti, M. Cuscunà, A. Valletta, L. Mariucci, A. Pecora, G. Fortunato, S. D. Brotherton, J. R. Ayres, "Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration," IEEE Trans. Electron Devices 50, 2425-2433 (2003).

2002 (2)

Y. Mishima, Y. Ebiko, "Improved lifetime of poly-Si TFTs with a self-aligned gate overlapped LDD structure," IEEE Trans. Electron Devices 49, 981-985 (2002).

J.-C. Goh, H.-J. Chung, J. Jang, C.-H. Han, "A new pixel circuit for active matrix organic light emitting diodes," IEEE Electron Device Lett. 23, 544-546 (2002).

1998 (1)

J. W. Lee, N. I. Lee, C. H. Han, "Improved stability of short-channel hydrogenated n-channel polycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide," IEEE Electron Device Lett. 19, 458-460 (1998).

1997 (1)

M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, I. Policicchio, "Floating body effects in polysilicon thin-film transistors," IEEE Trans. Electron Devices 44, 2234-2241 (1997).

1996 (1)

S. D. Brotherton, J. R. Ayres, M. J. Trainor, "Control and analysis of leakage currents in poly-Si TFTs," J. Appl. Phys. 79, 895-904 (1996).

1993 (1)

C. T. Liu, K. H. Lee, "An experimental study on the short channel effects in undergated polysilicon thin-film transistors with and without lightly doped drain structures," IEEE Electron Device Lett. 14, 149-151 (1993).

1988 (1)

J. P. Colinge, "Reduction of kink effect in thin-film SOI MOSFET's," IEEE Electron Device Lett. 9, 97-99 (1988).

1979 (1)

R. R. Troutman, "VLSI limitations from drain-induced barrier lowering," IEEE Trans. Electron Devices ED-26, 461-469 (1979).

Appl. Phys. Lett. (1)

A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M. Cuscunà, L. Maiolo, G. Fortunato, S. D. Brotherton, "Role of gate oxide thickness in controlling short channel effects in polycrystalline silicon thin film transistors," Appl. Phys. Lett. 85, 033507 (2009).

ECS Trans. (1)

G. Fortunato, M. Cuscunà, P. Gaucci, L. Maiolo, L. Mariucci, A. Pecora, A. Valletta, "Downscaling issues in polycrystalline silicon TFTs," ECS Trans. 33, 3-22 (2010).

IEEE Electron Device Lett. (5)

J. W. Lee, N. I. Lee, C. H. Han, "Improved stability of short-channel hydrogenated n-channel polycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide," IEEE Electron Device Lett. 19, 458-460 (1998).

C. T. Liu, K. H. Lee, "An experimental study on the short channel effects in undergated polysilicon thin-film transistors with and without lightly doped drain structures," IEEE Electron Device Lett. 14, 149-151 (1993).

J.-C. Goh, H.-J. Chung, J. Jang, C.-H. Han, "A new pixel circuit for active matrix organic light emitting diodes," IEEE Electron Device Lett. 23, 544-546 (2002).

J. P. Colinge, "Reduction of kink effect in thin-film SOI MOSFET's," IEEE Electron Device Lett. 9, 97-99 (1988).

J.-H. Lee, W.-J. Nam, B.-K. Kim, H.-S. Choi, Y.-M. Ha, M.-K. Han, "A new poly-Si TFT current-mirror pixel for active matrix organic light emitting diode," IEEE Electron Device Lett. 27, 830-833 (2004).

IEEE Trans. Electron Devices (7)

R. R. Troutman, "VLSI limitations from drain-induced barrier lowering," IEEE Trans. Electron Devices ED-26, 461-469 (1979).

M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, I. Policicchio, "Floating body effects in polysilicon thin-film transistors," IEEE Trans. Electron Devices 44, 2234-2241 (1997).

H. J. In, K. H. Oh, I. Lee, D. H. Ryu, S. M. Choi, K. N. Kim, H. D. Kim, O. K. Kwon, "An advanced external compensation system for active matrix organic light-emitting diode displays with poly-Si thin-film transistor backplane," IEEE Trans. Electron Devices 57, 3012-3019 (2010).

X. Guo, S. R. P. Silva, "Investigation on the current nonuniformity in current-mode TFT active-matrix display pixel circuitry," IEEE Trans. Electron Devices 52, 2379-2385 (2005).

Y. Mishima, Y. Ebiko, "Improved lifetime of poly-Si TFTs with a self-aligned gate overlapped LDD structure," IEEE Trans. Electron Devices 49, 981-985 (2002).

A. Valletta, L. Mariucci, G. Fortunato, "Hot-carrier-induced degradation of LDD polysilicon TFTs," IEEE Trans. Electron Devices 53, 43-50 (2006).

A. Bonfiglietti, M. Cuscunà, A. Valletta, L. Mariucci, A. Pecora, G. Fortunato, S. D. Brotherton, J. R. Ayres, "Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration," IEEE Trans. Electron Devices 50, 2425-2433 (2003).

J. Appl. Phys. (3)

S. D. Brotherton, J. R. Ayres, M. J. Trainor, "Control and analysis of leakage currents in poly-Si TFTs," J. Appl. Phys. 79, 895-904 (1996).

G. Kawachi, S. Tsuboi, T. Okada, M. Mitani, M. Matsumura, "Analysis of threshold voltage of short channel polycrystalline silicon thin-film transistors fabricated on large grains," J. Appl. Phys. 100, 114507 (2006).

A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M. Cuscunà, L. Maiolo, G. Fortunato, "Threshold voltage in short channel polycrystalline silicon thin film transistors: Influence of drain induced barrier lowering and floating body effects," J. Appl. Phys. 107, 074505 (2010).

J. Display Technol. (1)

Other (4)

A. Shin, B. Yoon, M. Y. Sung, "A novel current driving method using organic TFT pixel circuit for active-matrix OLED," Proc. IEEE Int. Conf. Microelectron. (2007) pp. 413-416.

F. H. Wang, H. C. Lin, P. S. Shih, L. Y. Lin, H. W. Liu, "New current programmed pixel circuit for active-matrix organic light-emitting-diode displays," Proc. IEEE Int. Conf. EDSSC (2007) pp. 1151-1154.

M. Hatano, H. Akimoto, T. Sakai, "A novel self-aligned gate overlapped LDD poly-Si TFT," Proc. IEDM 97 (1997) pp. 523-526.

C. Glasse, S. D. Brotherton, I. D. French, P. W. Green, C. Rowe, "Short channel LTPS TFTs made using sidewall spacer technology," Proc. Int. Workshop AMLCD 03 (2003) pp. 317.

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