Abstract

In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S.S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/decade and the threshold voltage V<sub>TH</sub> from 10.87 V to 5.00 V. Moreover, the threshold voltage V<sub>TH</sub> roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S.S. improvement due to a decreasing of the channel grain boundary trap density N<sub>t</sub>. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility μ<sub>FE</sub>. Therefore, the channel length dependence of field-effect mobility μ<sub>FE</sub> is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.

© 2011 IEEE

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  1. G. K. Guist, T. W. Sigmon, "High-performance thin-film transistors fabricated using excimer laser processing and grain engineering," IEEE Trans. Electron Devices 45, 925-932 (1998).
  2. Y. W. Choi, J. N. Lee, T. W. Jang, B. T. Ahn, "Thin-film transistors fabricated with poly-silicon films crystallized at low temperature by microwave annealing," IEEE Electron Device Lett. 20, 2-4 (1999).
  3. C. W. Lin, M. Z. Yang, C. C. Yeh, L. J. Cheng, T. Y. Huan, H. C. Cheng, H. C. Lin, T. S. Chao, C. Y. Chang, "Effects of plasma treatments, substrate types, and crystallization methods on performance and reliability of low temperature polysilicon TFTs," IEDM Tech. Dig. (1999) pp. 305-308.
  4. K. M. Chang, W. C. Yang, C. P. Tsai, "Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric," IEEE Electron Device Lett. 24, 512-514 (2003).
  5. J.-H. Jeon, M.-C. Lee, K.-C. Park, S.-H. Jung, M.-K. Han, "A new poly-Si TFT with selectively doped channel fabricated by novel excimer laser annealing," IEDM Tech. Dig. (2000) pp. 213-216.
  6. W. G. Hawkins, "Polycrystalline-silicon device technology for large-area electronics," IEEE Trans. Electron Devices 33, 477-481 (1986).
  7. T.-Y. Chiang, M.-W. Ma, Y.-H. Wu, P.-Y. Kuo, K.-T. Wang, C.-C. Liao, C.-R. Yeh, T.-S. Chao, "MILC-TFT with high-k dielectrics for one-time-programmable memory application," IEEE Electron Device Lett. 30, 954-956 (2009).
  8. T. T.-J. Wang, W. C.-Y. Ma, S.-W. Hung, C.-T. Kuo, "Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications," Thin Solid Films 518, 7429-7432 (2010).
  9. M.-W. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, T.-F. Lei, "Electrical characteristics of high performance SPC and MILC p-channel LTPS-TFT with high- gate dielectric," Electrochem. and Solid State Lett. 12, H361-H364 (2009).
  10. M.-W. Ma, T.-Y. Chiang, W.-C. Wu, T.-S. Chao, T.-F. Lei, "Characteristics of ${\hbox{HfO}}_{2}$/poly-Si interfacial layer on CMOS LTPS-TFTs with ${\hbox{HfO}}_{2}$ gate dielectric and ${\hbox{O}}_{2}$ plasma surface treatment," IEEE Trans. Electron Devices 55, 3489-3493 (2008).
  11. I.-W. Wu, T.-Y. Huang, W. B. Jackson, A. G. Lewis, A. C. Chiang, "Passivation kinetics of two types of defects in polysilicon TFI by plasma hydrogenation," IEEE Electron Device Lett. 12, 181-183 (1991).
  12. C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitrious, N. Economou, "Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures," IEEE Trans. Electron Devices 39, 598-606 (1992).
  13. J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys. 53, 1193-1202 (1982).
  14. R. E. Proano, R. S. Misage, D. G. Ast, "Development and electrical properties of undoped polycrystalline silicon thin-film transistor," IEEE Trans. Electron Devices 36, 1915-1922 (1989).
  15. A. Valletta, L. Mariucci, G. Fortunato, "Surface-scattering effects in polycrystalline silicon thin-film transistors," Appl. Phys. Lett. 82, 3119-3121 (2003).
  16. P. Gaucci, A. Valletta, L. Mariucci, G. Fortunato, S. D. Brotherton, "Numerical simulation of parasitic resistance effects in polycrystalline silicon TFTs," IEEE Trans. Electron Devices 53, 573-577 (2006).
  17. C.-Y. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, T.-F. Lei, "Channel film thickness effect of low-temperature polycrystalline-silicon thin-film transistors," IEEE Trans. Electron Devices 58, 1268-1272 (2011).

2011 (1)

C.-Y. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, T.-F. Lei, "Channel film thickness effect of low-temperature polycrystalline-silicon thin-film transistors," IEEE Trans. Electron Devices 58, 1268-1272 (2011).

2010 (1)

T. T.-J. Wang, W. C.-Y. Ma, S.-W. Hung, C.-T. Kuo, "Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications," Thin Solid Films 518, 7429-7432 (2010).

2009 (2)

M.-W. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, T.-F. Lei, "Electrical characteristics of high performance SPC and MILC p-channel LTPS-TFT with high- gate dielectric," Electrochem. and Solid State Lett. 12, H361-H364 (2009).

T.-Y. Chiang, M.-W. Ma, Y.-H. Wu, P.-Y. Kuo, K.-T. Wang, C.-C. Liao, C.-R. Yeh, T.-S. Chao, "MILC-TFT with high-k dielectrics for one-time-programmable memory application," IEEE Electron Device Lett. 30, 954-956 (2009).

2008 (1)

M.-W. Ma, T.-Y. Chiang, W.-C. Wu, T.-S. Chao, T.-F. Lei, "Characteristics of ${\hbox{HfO}}_{2}$/poly-Si interfacial layer on CMOS LTPS-TFTs with ${\hbox{HfO}}_{2}$ gate dielectric and ${\hbox{O}}_{2}$ plasma surface treatment," IEEE Trans. Electron Devices 55, 3489-3493 (2008).

2006 (1)

P. Gaucci, A. Valletta, L. Mariucci, G. Fortunato, S. D. Brotherton, "Numerical simulation of parasitic resistance effects in polycrystalline silicon TFTs," IEEE Trans. Electron Devices 53, 573-577 (2006).

2003 (2)

A. Valletta, L. Mariucci, G. Fortunato, "Surface-scattering effects in polycrystalline silicon thin-film transistors," Appl. Phys. Lett. 82, 3119-3121 (2003).

K. M. Chang, W. C. Yang, C. P. Tsai, "Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric," IEEE Electron Device Lett. 24, 512-514 (2003).

1999 (1)

Y. W. Choi, J. N. Lee, T. W. Jang, B. T. Ahn, "Thin-film transistors fabricated with poly-silicon films crystallized at low temperature by microwave annealing," IEEE Electron Device Lett. 20, 2-4 (1999).

1998 (1)

G. K. Guist, T. W. Sigmon, "High-performance thin-film transistors fabricated using excimer laser processing and grain engineering," IEEE Trans. Electron Devices 45, 925-932 (1998).

1992 (1)

C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitrious, N. Economou, "Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures," IEEE Trans. Electron Devices 39, 598-606 (1992).

1991 (1)

I.-W. Wu, T.-Y. Huang, W. B. Jackson, A. G. Lewis, A. C. Chiang, "Passivation kinetics of two types of defects in polysilicon TFI by plasma hydrogenation," IEEE Electron Device Lett. 12, 181-183 (1991).

1989 (1)

R. E. Proano, R. S. Misage, D. G. Ast, "Development and electrical properties of undoped polycrystalline silicon thin-film transistor," IEEE Trans. Electron Devices 36, 1915-1922 (1989).

1986 (1)

W. G. Hawkins, "Polycrystalline-silicon device technology for large-area electronics," IEEE Trans. Electron Devices 33, 477-481 (1986).

1982 (1)

J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys. 53, 1193-1202 (1982).

Appl. Phys. Lett. (1)

A. Valletta, L. Mariucci, G. Fortunato, "Surface-scattering effects in polycrystalline silicon thin-film transistors," Appl. Phys. Lett. 82, 3119-3121 (2003).

Electrochem. and Solid State Lett. (1)

M.-W. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, T.-F. Lei, "Electrical characteristics of high performance SPC and MILC p-channel LTPS-TFT with high- gate dielectric," Electrochem. and Solid State Lett. 12, H361-H364 (2009).

IEEE Electron Device Lett. (4)

I.-W. Wu, T.-Y. Huang, W. B. Jackson, A. G. Lewis, A. C. Chiang, "Passivation kinetics of two types of defects in polysilicon TFI by plasma hydrogenation," IEEE Electron Device Lett. 12, 181-183 (1991).

Y. W. Choi, J. N. Lee, T. W. Jang, B. T. Ahn, "Thin-film transistors fabricated with poly-silicon films crystallized at low temperature by microwave annealing," IEEE Electron Device Lett. 20, 2-4 (1999).

K. M. Chang, W. C. Yang, C. P. Tsai, "Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric," IEEE Electron Device Lett. 24, 512-514 (2003).

T.-Y. Chiang, M.-W. Ma, Y.-H. Wu, P.-Y. Kuo, K.-T. Wang, C.-C. Liao, C.-R. Yeh, T.-S. Chao, "MILC-TFT with high-k dielectrics for one-time-programmable memory application," IEEE Electron Device Lett. 30, 954-956 (2009).

IEEE Trans. Electron Devices (7)

G. K. Guist, T. W. Sigmon, "High-performance thin-film transistors fabricated using excimer laser processing and grain engineering," IEEE Trans. Electron Devices 45, 925-932 (1998).

W. G. Hawkins, "Polycrystalline-silicon device technology for large-area electronics," IEEE Trans. Electron Devices 33, 477-481 (1986).

C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitrious, N. Economou, "Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures," IEEE Trans. Electron Devices 39, 598-606 (1992).

M.-W. Ma, T.-Y. Chiang, W.-C. Wu, T.-S. Chao, T.-F. Lei, "Characteristics of ${\hbox{HfO}}_{2}$/poly-Si interfacial layer on CMOS LTPS-TFTs with ${\hbox{HfO}}_{2}$ gate dielectric and ${\hbox{O}}_{2}$ plasma surface treatment," IEEE Trans. Electron Devices 55, 3489-3493 (2008).

P. Gaucci, A. Valletta, L. Mariucci, G. Fortunato, S. D. Brotherton, "Numerical simulation of parasitic resistance effects in polycrystalline silicon TFTs," IEEE Trans. Electron Devices 53, 573-577 (2006).

C.-Y. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, T.-F. Lei, "Channel film thickness effect of low-temperature polycrystalline-silicon thin-film transistors," IEEE Trans. Electron Devices 58, 1268-1272 (2011).

R. E. Proano, R. S. Misage, D. G. Ast, "Development and electrical properties of undoped polycrystalline silicon thin-film transistor," IEEE Trans. Electron Devices 36, 1915-1922 (1989).

J. Appl. Phys. (1)

J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys. 53, 1193-1202 (1982).

Thin Solid Films (1)

T. T.-J. Wang, W. C.-Y. Ma, S.-W. Hung, C.-T. Kuo, "Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications," Thin Solid Films 518, 7429-7432 (2010).

Other (2)

J.-H. Jeon, M.-C. Lee, K.-C. Park, S.-H. Jung, M.-K. Han, "A new poly-Si TFT with selectively doped channel fabricated by novel excimer laser annealing," IEDM Tech. Dig. (2000) pp. 213-216.

C. W. Lin, M. Z. Yang, C. C. Yeh, L. J. Cheng, T. Y. Huan, H. C. Cheng, H. C. Lin, T. S. Chao, C. Y. Chang, "Effects of plasma treatments, substrate types, and crystallization methods on performance and reliability of low temperature polysilicon TFTs," IEDM Tech. Dig. (1999) pp. 305-308.

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