Abstract

In this paper, an intra-panel interface with a clock embedded differential signaling for TFT-LCD systems is proposed. The proposed interface reduces the number of signal lines between the timing controller and the column drivers in a TFT-LCD panel by adopting the embedded clock scheme. The protocol of the proposed interface provides a delay-locked loop (DLL)-based clock recovery scheme for the receiver. The timing controller and the column driver integrated with the proposed interface are fabricated in 0.13-µm CMOS process technology and 0.18-µm high voltage CMOS process technology, respectively. The proposed interface is verified on a 47-inch Full High-Definition (FHD) (1920RGB x 1080) TFT-LCD panel with 8-bit RGB and 120-Hz driving technology. The maximum data rate per differential pair was measured to be as high as 2.0 Gb/s in a wafer test.

© 2011 IEEE

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  1. VESA and Industry Standards and Guidelines for Computer Display Monitor Timing 1.0, Rev. 0.8VESA (1998).
  2. C. S. Jang, J. C. Choi, J. H. Park, I. J. Chung, O. K. Kwon, "An intra interface of flat panel displays for high-end TV applications," IEEE Trans. Consumer Electron. 54, 1447-1452 (2008).
  3. “RSDS™Intra-Panel Interface Specification 1.0National Semiconductor Company (2003) http://www.national.com/appinfo/fpd/files/RSDS_V095.PDF.
  4. “mini-LVDS Interface Specification,” SLDA007A: Application Report Texas Instruments IncorporatedDallas (Texas Instruments Incorporated, 2003) http://focus.ti.com/lit/an/slda007a/slds007a.pdf.
  5. R. I. McCartney, M. Bell, "A third generation timing controller and column driver architecture using point-to-point differential signaling," SID Symp. Dig. Tech. Papers (2004) pp. 1556-1559.
  6. K. Nakajima, Y. Hori, T. Nose, K. Umeda, J. Ishii, "A 12-bit LCD source driver IC with point-to-point link interface," SID Symp. Dig. Tech. Papers (2007) pp. 1633-1636.
  7. M. J. Park, Y. J. Lee, J. H. Lim, B. I. Hong, T. S. Kim, H. S. Nam, H. S. Song, D. K. Jeong, W. C. Kim, "An advanced intra-panel interface (AiPi) with clock embedded multi-level point-to-point differential signaling for large-sized TFT-LCD applications," SID Symp. Dig. Tech. Papers (2006) pp. 1502-1505.
  8. K. Yamaguchi, Y. Hori, K. Nakajima, K. Suzuki, M. Mizuno, H. Hayama, "A 2.0 Gb/s clock-embedded interface for full-HD 10 b 120 Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery," IEEE Int. Solid-State Circuits Conf. (ISSCC) 2009 Dig. Tech. Papers (2009) pp. 192-194.
  9. H. K. Jeon, Y. W. Moon, J. I. Seo, J. H. Na, H. S. Oh, D. K. Han, P. S. Kang, Y. S. Jeong, M. G. Park, S. C. O, J. C. Hong, L. S. Kim, "A clock embedded differential signaling (CEDS™) for the next generation TFT-LCD applications," SID Symp. Dig. Tech. Papers (2009) pp. 975-978.
  10. S. Ozawa, S. Miura, S. Kousokabe, Y. Ishizone, S. Tomosqi, J. I. Okamura, "A wide band CDR for digital video data transition," IEEE Asian Solid-State Circuits Conf. (ASSCC) (2005) pp. 33-36.
  11. National Semiconductor Company“FPD-Link II Display SerDes Overview,” AN-1807: Application Note 1907 (2008) http://www.national.com/an/AN/AN-1807.pdf.
  12. C.-K. K. Yang, Phase-Locking in High-Performance Systems From Devices to Architectures (IEEE Press, 2003) pp. 13-22.
  13. W. J. Choe, B. J. Lee, J. H. Lee, D. K. Jeong, G. D. Kim, "A single-pair serial link for mobile displays with clock edge modulation scheme," IEEE J. Solid-State Circuits 42, 2012-2020 (2007).
  14. S. Sidiropoulos, M. A. Horowitz, "A semidigital dual delay locked loop," IEEE J. Solid-State Circuits 32, 1683-1692 (1997).
  15. J. Lee, K. S. Kundert, B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits," IEEE J. Solid-State Circuits 39, 1571-1580 (2004).

2008 (1)

C. S. Jang, J. C. Choi, J. H. Park, I. J. Chung, O. K. Kwon, "An intra interface of flat panel displays for high-end TV applications," IEEE Trans. Consumer Electron. 54, 1447-1452 (2008).

2007 (1)

W. J. Choe, B. J. Lee, J. H. Lee, D. K. Jeong, G. D. Kim, "A single-pair serial link for mobile displays with clock edge modulation scheme," IEEE J. Solid-State Circuits 42, 2012-2020 (2007).

2004 (1)

J. Lee, K. S. Kundert, B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits," IEEE J. Solid-State Circuits 39, 1571-1580 (2004).

1997 (1)

S. Sidiropoulos, M. A. Horowitz, "A semidigital dual delay locked loop," IEEE J. Solid-State Circuits 32, 1683-1692 (1997).

IEEE J. Solid-State Circuits (3)

W. J. Choe, B. J. Lee, J. H. Lee, D. K. Jeong, G. D. Kim, "A single-pair serial link for mobile displays with clock edge modulation scheme," IEEE J. Solid-State Circuits 42, 2012-2020 (2007).

S. Sidiropoulos, M. A. Horowitz, "A semidigital dual delay locked loop," IEEE J. Solid-State Circuits 32, 1683-1692 (1997).

J. Lee, K. S. Kundert, B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits," IEEE J. Solid-State Circuits 39, 1571-1580 (2004).

IEEE Trans. Consumer Electron. (1)

C. S. Jang, J. C. Choi, J. H. Park, I. J. Chung, O. K. Kwon, "An intra interface of flat panel displays for high-end TV applications," IEEE Trans. Consumer Electron. 54, 1447-1452 (2008).

Other (11)

“RSDS™Intra-Panel Interface Specification 1.0National Semiconductor Company (2003) http://www.national.com/appinfo/fpd/files/RSDS_V095.PDF.

“mini-LVDS Interface Specification,” SLDA007A: Application Report Texas Instruments IncorporatedDallas (Texas Instruments Incorporated, 2003) http://focus.ti.com/lit/an/slda007a/slds007a.pdf.

R. I. McCartney, M. Bell, "A third generation timing controller and column driver architecture using point-to-point differential signaling," SID Symp. Dig. Tech. Papers (2004) pp. 1556-1559.

K. Nakajima, Y. Hori, T. Nose, K. Umeda, J. Ishii, "A 12-bit LCD source driver IC with point-to-point link interface," SID Symp. Dig. Tech. Papers (2007) pp. 1633-1636.

M. J. Park, Y. J. Lee, J. H. Lim, B. I. Hong, T. S. Kim, H. S. Nam, H. S. Song, D. K. Jeong, W. C. Kim, "An advanced intra-panel interface (AiPi) with clock embedded multi-level point-to-point differential signaling for large-sized TFT-LCD applications," SID Symp. Dig. Tech. Papers (2006) pp. 1502-1505.

K. Yamaguchi, Y. Hori, K. Nakajima, K. Suzuki, M. Mizuno, H. Hayama, "A 2.0 Gb/s clock-embedded interface for full-HD 10 b 120 Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery," IEEE Int. Solid-State Circuits Conf. (ISSCC) 2009 Dig. Tech. Papers (2009) pp. 192-194.

H. K. Jeon, Y. W. Moon, J. I. Seo, J. H. Na, H. S. Oh, D. K. Han, P. S. Kang, Y. S. Jeong, M. G. Park, S. C. O, J. C. Hong, L. S. Kim, "A clock embedded differential signaling (CEDS™) for the next generation TFT-LCD applications," SID Symp. Dig. Tech. Papers (2009) pp. 975-978.

S. Ozawa, S. Miura, S. Kousokabe, Y. Ishizone, S. Tomosqi, J. I. Okamura, "A wide band CDR for digital video data transition," IEEE Asian Solid-State Circuits Conf. (ASSCC) (2005) pp. 33-36.

National Semiconductor Company“FPD-Link II Display SerDes Overview,” AN-1807: Application Note 1907 (2008) http://www.national.com/an/AN/AN-1807.pdf.

C.-K. K. Yang, Phase-Locking in High-Performance Systems From Devices to Architectures (IEEE Press, 2003) pp. 13-22.

VESA and Industry Standards and Guidelines for Computer Display Monitor Timing 1.0, Rev. 0.8VESA (1998).

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